A45L9332AE-6 AMIC Technology, Corp., A45L9332AE-6 Datasheet - Page 18

• Manufacturer Part Number: A45L9332AE-6
• Description: 256K x 32 Bit x 2 Banks Synchronous Graphic RAM
• Manufacturer: AMIC Technology, Corp.

Device Operations (continued)
Write Per Bit
Write per bit (i.e. I/O mask mode) for SGRAM is a function
that selectively masks bits of data being written to the
devices. The mask is stored in an internal register and
applied to each bit of data written when enabled. Bank
active command with DSF = High enabled write per bit
operations is stored in the mask register accessed by
SWCBR (Special Mode Register Set Command). When a
mask bit = 1, the associated data bit is written when a write
command is executed and write per bit has been enabled
for the bank being written. When a mask bit = 0, the
associated data bit is unaltered when a write command is
executed and the write per bit has been enabled for the
bank being written. No additional timing conditions are
required for write per bit operations. Write per bit writes can
be either single write, burst writes or block writes. DQM
masking is the same for write per bit and non-WPB write.
Block Write
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during
a single access cycle. During block write the data to be
written comes from an internal “color” register and DQ I/O
pins are used for independent column selection. The block
of column to be written is aligned on 8 column boundaries
and is defined by the column address with the 3 LSB’s
ignored. Write command with DSF = 1enables block write
for the associated bank. A write command with DSF = 0
enables normal write for the associated bank. The block
width is 8 column where column = “n” bits for by “n” part.
The color register is the same width as the data port of the
chip. It is written via a SWCBR where data present on the
DQ pin is to be coupled into the internal color register. The
color register provides the data masked by the DQ column
select, WPB mask (If enabled), and DQM byte mask.
Column data masking (Pixel masking) is provided on an
individual column basis for each byte of data. The column
mask is driven on the DQ pins during a block write
command. The DQ column mask function is segmented on
a per bit basis (i.e. DQ[0:7] provides the column mask for
data bits[0:7], DQ[8:15] provides the column mask for data
bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data its [8:15], etc). Block writes are
always non-burst, independent of the burst length that has
been programmed into the mode register. Back to back
block writes are allowed provided that the specified block
write cycle time (t
enabled by the bank active command with DSF = 1, then
write per bit masking of the color register data is enabled.
If write per bit was disabled by a bank active command with
DSF = 0, the write per bit masking of the color register data
is disabled. DQM masking provides independent data byte
masking during block write exactly the same as it does
during normal write operations, except that the control is
extended to the consecutive 8 columns of the block write.
PRELIMINARY
(October, 2001, Version 0.1)
BWC
) is satisfied. If write per bit was
17
Timing Diagram to Illustrate t
Clock
CKE
RAS
CAS
DSF
WE
CS
0
AMIC Technology, Inc.
1 CLK BW
A45L9332A Series
BWC
1
High
2