MPC8321E Freescale Semiconductor, Inc, MPC8321E Datasheet - Page 12

• Manufacturer Part Number: MPC8321E
• Description: Mpc8321e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
5
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8323E.
component(s).
Table 10
12
Required assertion time of HRESET or SRESET (input) to activate reset
flow
Required assertion time of PORESET with stable clock applied to CLKIN
when the MPC8323E is in PCI host mode
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the MPC8323E is in PCI agent mode
HRESET/SRESET assertion (output)
HRESET negation to SRESET negation (output)
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI host mode
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI agent mode
Input hold time for POR config signals with respect to negation of
HRESET
Time for the MPC8323E to turn off POR configuration signals with respect
to the assertion of HRESET
Time for the MPC8323E to turn on POR configuration signals with respect
to the negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details.
the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details.
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
PCI_SYNC_IN
CLKIN
RESET Initialization
is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See
provides the PLL lock times.
is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the
Table 9
Parameter/Condition
Parameter/Condition
provides the reset initialization AC timing specifications for the reset
Table 9. RESET Initialization Timing Specifications
Table 10. PLL Lock Times
Min
Min
—
512
32
32
32
16
—
4
4
0
1
Max
—
—
—
—
—
—
—
—
—
4
Max
100
Freescale Semiconductor
t
t
t
t
t
t
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
t
t
CLKIN
CLKIN
Unit
ns
ns
Unit
μs
Notes
Notes
1, 3
1
2
1
1
1
2
1
3