MPC8321E Freescale Semiconductor, Inc, MPC8321E Datasheet - Page 9

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MPC8321E

Manufacturer Part Number
MPC8321E
Description
Mpc8321e Powerquicc Ii Pro Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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2.1.4
Table 4
2.2
During power ramp up, before the power supplies are stable, there might be a period of time that I/O pins
are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are
three-stated. In order to minimize the time that I/O pins being actively driven, it is required to apply the
core voltage before the I/O voltage and assert PORESET before the power supplies fully ramp up. The
core voltage (Vdd) should reach its nominal level before the I/O voltage (OVdd and GVdd) reaches 0.7 V.
In addition, the I/O voltage should reach its nominal level within 100 microseconds after the core voltage
has reached its nominal level (see
requirements are not met.
Note that there is no specific power down sequence requirement for the MPC8323E.
Freescale Semiconductor
Input capacitance for all pins except CLKIN
Input capacitance for CLKIN
Note:
1. The external clock generator should be able to drive 10 pF.
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
describes the input capacitance for the CLKIN pin in the MPC8323E.
Power Sequencing
Input Capacitance Specification
0.7 V
V
Parameter/Condition
0
Table 4. Input Capacitance Specification
Figure 4. MPC8323E Power Sequencing
Figure
Min
4). Excessive current consumption may be observed if these
100 μs
Max
Symbol
C
ICLKIN
C
I/O Voltage (GV
I
Min
10
6
DD
Core Voltage (V
and OV
Max
DD
8
) 3.3 V
DD
Electrical Characteristics
) 1 V
t
Unit
pF
pF
Notes
1
9

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