MT16JSF25664HZ Micron Semiconductor Products, MT16JSF25664HZ Datasheet - Page 4

• Manufacturer Part Number: MT16JSF25664HZ
• Description: Ddr3 Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 6: Pin Descriptions
PDF: 09005aef83364b70
jsf16c256_512x64hz.pdf - Rev. B 12/09
RAS#, CAS#,
DQS#[7:0]
DQS[7:0],
ODT[1:0]
DQ[63:0]
Symbol
CK#[1:0]
CKE[1:0]
CK[1:0],
DM[7:0]
EVENT#
BA[2:0]
A[14:0]
RESET#
SA[1:0]
S#[1:0]
WE#
SDA
V
SCL
DD
(open drain)
(LVCMOS)
Output
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selec-
ted by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS
commands. The address inputs also provide the op-code during the mode register com-
mand set. A[12:0] address the 1Gb DDR3 devices. A[13:0] address the 1Gb DDR3 devices.
A[14:0] address the 2Gb DDR3 devices.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins.
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
Reset: RESET# is an active LOW CMOS input referenced to V
a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command de-
coder.
Presence-detect address inputs: These pins are used to configure the temperature sensor/
SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize communication to and from
the temperature sensor/SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply: 1.5V ±0.075V.
DD
. RESET# assertion and deassertion are asynchronous.
2GB, 4GB (x64, DR) 204-Pin Halogen-Free DDR3 SODIMM
4
2
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
2
C bus.
. The RESET# input receiver is
© 2009 Micron Technology, Inc. All rights reserved.
DD
and DC LOW ≤ 0.2 ×