MT16JSF25664HZ Micron Semiconductor Products, MT16JSF25664HZ Datasheet - Page 9

• Manufacturer Part Number: MT16JSF25664HZ
• Description: Ddr3 Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

General Description
Fly-By Topology
Electrical Specifications
Table 9: Absolute Maximum Ratings
Table 10: Operating Conditions
PDF: 09005aef83364b70
jsf16c256_512x64hz.pdf - Rev. B 12/09
Sym-
bol
V
I
V
VTT
DD
TT
V
Symbol
IN
V
, V
DD
Parameter
V
Termination reference current from V
Termination reference voltage (DC) –
command/address bus
OUT
DD
supply voltage
Parameter
V
Voltage on any pin relative to V
DD
supply voltage relative to V
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially an 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device’s data sheet is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
2GB, 4GB (x64, DR) 204-Pin Halogen-Free DDR3 SODIMM
TT
SS
SS
0.49 × V
1.425
–600
Min
DD
9
- 20mV
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Min
–0.4
–0.4
0.5 × V
Nom
1.5
–
DD
0.51 × V
+1.975
+1.975
Max
1.575
Max
+600
General Description
DD
© 2009 Micron Technology, Inc. All rights reserved.
+ 20mV
Units
mA
V
V
Units
V
V
Notes
1