HMP8115 Intersil Corporation, HMP8115 Datasheet
HMP8115
Related parts for HMP8115
HMP8115 Summary of contents
Page 1
... CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Description ) PAL Operation The HMP8115 is a high quality NTSC and PAL decoder with C internal A/D converters compatible with NTSC M, PAL and combination N (N Both composite and S-video (Y/C) input formats are sup- ported. A 2-line comb fi ...
Page 2
... BT.656 CLOSED CAPTIONING AND WIDE SCREEN SIGNALLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TELETEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REAL TIME CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HMP8115 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RELATED APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HMP8115 HMP8115 2 PAGE ...
Page 3
... HMP8115 3 ...
Page 4
Functional Block Diagram (Continued) CLK (24.54, 27.0 OR 29.5MHz) 4FSC CLOCK CHROMA PLL NCO CLK TO 4FSC RATIO CR[7:0] C,CVBS C,CVBS C DATA DATA LINE M DELAY U COMB X FILTER INPUT SAMPLE RATE CONVERTER Y DATA Y DATA Y,CVBS ...
Page 5
... PLL is used to maintain vertical spatial alignment. The PLLs are designed to maintain lock even in the event of VCR headswitches and multipath noise. The HMP8115 contains two 8-bit A/D converters and an I interface for programming internal registers. External Video Processing Before a video signal can be digitized the decoder has some external processing considerations that need to be addressed ...
Page 6
... A composite video signal has the luma (Y) and chroma (C) information mixed in the same video signal. The Y/C separa- tion process is responsible for separating the composite video signal into these two components. The HMP8115 uti- lizes a comb filter to minimize the artifacts that are associ- ated with the Y/C separation process. ...
Page 7
... C Digital Processing of Video Once the luma and chroma have been separated the HMP8115 then performs programmable modifications (i.e. contrast, coring, color space conversions, color AGC, etc.) to the decoded video signal CbCr CONVERSION The baseband U and V signals are scaled and offset to gen- erate a nominal range of 16-240 for both the Cb and Cr data ...
Page 8
... The 16-bit data may be converted to 16-bit linear RGB, using the following equations. Although the PAL speci- fications specify a gamma of 2.8, a gamma of 2.2 is normally used. The HMP8115 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: for R B < 0.0812*31, G < 0.0812* (31)((R /31)/4 ...
Page 9
... The trailing edge of VSYNC clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field. FIGURE 6. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION HMP8115 a fixed latency due to internal pipeline processing. The pulse width of the HSYNC is defi ...
Page 10
... H format sections that follow for the specific behavior for DVALID. BLANK is used to determine if the HMP8115 is generating active video data. BLANK should be used in conjunction with DVALID to capture digital data from the decoder. BLANK, DVALID and the video data are output after the internal pipe- line latency and synchronous with the rising edge of CLK2 ...
Page 11
... CLK2 is exactly 2x the desired output sample rate. DVALID being asserted indicates valid pixel data is present on the P15-P8 pixel outputs. DVALID is never asserted during the blanking intervals. Refer to Figure 10. HMP8115 ODD FIELD SYNC AND BACK PORCH ...
Page 12
... Figures 12 and 13. If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the same as the first mode, with the exception that DVALID does not have a 50% duty cycle. This mode is intended for back- ward compatibility with HMP8112(A) timing dependencies in HMP8115 ...
Page 13
... DVLD NOTE: 13. BLANK is asserted per Figure 9. FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0) HMP8115 BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. When BLANK is asserted and VBIVALID is deasserted, the YCbCr outputs have a value of 16 for Y and 128 for Cb and Cr; the RGB out- puts have a value of 0 ...
Page 14
... BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. For proper operation, CLK2 must be exactly 2x the desired output sample rate. The DVALID output is continuously asserted during the entire active video time. HMP8115 ...
Page 15
... V: “1” during vertical blanking 25. H: “0” at SAV (start of active video); “1” at EAV (end of active video) Advanced Features In addition to digitizing an analog video signal the HMP8115 has hardware to process different types of Vertical Blanking Interval (VBI) data as described in the following sections. ...
Page 16
... WSS information are monitored. If WSS is enabled and WSS data is present, the WSS data is loaded into the WSS data registers. HMP8115 Detection of WSS The WSS decoder monitors the appropriate scan lines look- ing for the run-in and start codes used by WSS. If found, it ...
Page 17
... WSS_EVEN_A and WSS_EVEN_B registers set to “0” after the data has been read out. BT.656 ANCILLARY DATA Through the BT.656 interface the HMP8115 can generate non-active video data which contains CC, WSS, teletext or CLK VBIVALID ...
Page 18
... WSS CRC data = “00 0000” during PAL operation. 32. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. TELETEXT The HMP8115 supports ITU-R BT.653 625-line and 525-line teletext system B, C and D capture. NABTS (North American Broadcast Teletext Specification) is the same as BT.653 525- line system C, which is also used to transmit Intel Intercast™ ...
Page 19
... P8-P13. 37. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. 38. For 525-line system B, bits 280-343 are “0”. 39. For system C, bits 272-343 are “0”. HMP8115 DATA PACKET Bit 0 FIGURE 18. TELETEXT VBI VIDEO SIGNAL ...
Page 20
... P8-P13. 41. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. HMP8115 The PSW bit is always a “0” for NTSC encoding. During PAL encoding, it indicates the sign of V (“0” = negative; “1” = pos- itive) for that scan line ...
Page 21
... The bit descriptions of the control registers are listed in Tables 9-48. The HMP8115 supports the fast-mode (up to 400 kbps) I interface consisting of the SDA and SCL pins. The device acts as a slave for receiving and transmitting data over the serial interface ...
Page 22
... HMP8115 Control Registers SUB- ADDRESS CONTROL REGISTER 00 PRODUCT INPUT FORMAT H 02 OUTPUT FORMAT H 03 OUTPUT CONTROL H 04 GENLOCK CONTROL H 05 ANALOG INPUT CONTROL H 06 COLOR PROCESSING H 07 RESERVED H 08 LUMA PROCESSING H 09 Reserved H 0A SLICED VBI DATA ENABLE H 0B SLICED VBI DATA OUTPUT ...
Page 23
... -7F Test and Unused H H BIT NO. FUNCTION 7-0 Product ID BIT NO. FUNCTION 7 Reserved 6-5 Video Timing Standard 4 Auto Detect Video Standard 3 Setup Select 2-0 Reserved HMP8115 RESET/ DEFAULT USE VALUE VALUE 4A Table Table Table Table Table Table Table 2 ...
Page 24
... Active low (low during valid pixel data Active high (high during valid pixel data) 0 VBIVALID 0 = Active low (low during VBI data) Polarity 1 = Active high (high during VBI data) HMP8115 TABLE 12. OUTPUT FORMAT REGISTER SUB ADDRESS = 02 H DESCRIPTION 000 = 16-bit 4:2:2 YCbCr 001 = 8-bit 4:2:2 YCbCr 010 = 8-bit BT ...
Page 25
... TABLE 15. ANALOG INPUT CONTROL REGISTER BIT NO. FUNCTION 7-3 Reserved 2-0 Video Signal 000 = NTSC/PAL 1 Input Select 001 = NTSC/PAL 2 010 = NTSC/PAL 3 011 = S-video 100 = reserved 101 = reserved 110 = reserved 111 = reserved HMP8115 SUB ADDRESS = 04 H DESCRIPTION SUB ADDRESS = 05 H DESCRIPTION 25 RESET STATE ...
Page 26
... Sharpness If a value of “01” or “10”, the sharpness adjust register is used to specify the amount of Frequency Select sharpness to be applied Bypass sharpness control 01 = Maximum gain at 2.6MHz 10 = Maximum gain at color subcarrier frequency 11 = reserved HMP8115 SUB ADDRESS = 06 H DESCRIPTION SUB ADDRESS = 08 H DESCRIPTION 26 ...
Page 27
... Do not output as BT.656 ancillary 1 = Output as BT.656 ancillary data 4-1 Reserved 0 RTCI This bit specifies whether or not to output RTCI data as BT.656 ancillary data. BT.656 Output not output as BT.656 ancillary Enable 1 = Output as BT.656 ancillary data HMP8115 SUB ADDRESS = 0A H DESCRIPTION ) PAL C ) PAL C ) PAL C ) PAL ...
Page 28
... Input Video This bit is read-only. Data written to this bit is ignored. Detect Status 0 = Input video not detected on selected video input 1 = Input video detected on selected video input 3-0 Reserved HMP8115 TABLE 20. VBI DATA STATUS REGISTER SUB ADDRESS = 0C H DESCRIPTION TABLE 21. VIDEO STATUS REGISTER SUB ADDRESS = 0E ...
Page 29
... Reserved 0 Vertical Sync If this bit is a “1”, the reason for the interrupt request was that a new field was started. To Interrupt Status clear the interrupt request, a “1” must be written to this bit. HMP8115 SUB ADDRESS = 0F H DESCRIPTION SUB ADDRESS = 10 H DESCRIPTION ...
Page 30
... Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A value of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharp- ness mode selection is “disable sharpness control” or “reserved”. HMP8115 TABLE 24. BRIGHTNESS REGISTER SUB ADDRESS = 18 ...
Page 31
... If even field captioning is enabled and present, this register is loaded with the first eight Caption Data bits of caption data on line 281, 284, or 335. Bit 0 corresponds to the first bit of caption information. Data written to this register is ignored. HMP8115 TABLE 30. HOST CONTROL REGISTER SUB ADDRESS = 1F H ...
Page 32
... Reserved 13-8 Even Field If even field WSS is enabled and present, this register is loaded with the second six bits WSS Data of WSS information on line 280, 283, or 336. Data written to this register is ignored. HMP8115 SUB ADDRESS = 23 H DESCRIPTION TABLE 35. WSS_ODD_A DATA REGISTER SUB ADDRESS = 24 ...
Page 33
... It specifies the line number to assert BLANK each field. For NTSC operation, it occurs on line ( odd fields and line (n + 268) on even fields. For PAL operation, it occurs on line ( odd fields and line (n + 318) on even fields. HMP8115 SUB ADDRESS = 29 H DESCRIPTION ...
Page 34
... If the horizontal sync pulse falls inside this window, the digital PLL will lock to it. If the hor- izontal sync pulse falls outside this window, the digital PLL is immediately reset to have the same timing. Recommend using a value of 20 HMP8115 SUB ADDRESS = 34 H DESCRIPTION TABLE 46 ...
Page 35
... Pinout AGND VAA AGND NC NTSC/PAL3 NTSC/PAL2 NTSC/PAL1 YIN YOUT AGND AGND VAA CLK2 VAA AGND AGND A/D_TEST AGND HMP8115 80 LEAD PQFP TOP VIEW ...
Page 36
... NTSC/PAL 1 7 NTSC/PAL 2 6 NTSC/PAL 3 5 (Y) HMP8115 O Pixel output pins. See Table 3. O Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The polarity of HSYNC is programmable. This pin is three-stated after a RESET or soft- ware reset and should be pulled high through a 10K resistor. ...
Page 37
... A/D TEST 18, 20, 32, 73, 74 HMP8115 I Chrominance (C) video input. This input must be AC-coupled to the video signal (us- ing capacitor) and terminated with a 75 resistor, as shown in the Applications section. These components, and the corresponding anti-aliasing lowpass filter, should be as close to this pin as possible for best performance. If not used, this pin should be connected to AGND through a 0.1 F capacitor. Analog output of the video multiplexer. This output should be lowpass fi ...
Page 38
... EVALUATION BOARD HMPVIDEVAL/ISA The HMPVIDEVAL/ISA evaluation board allows connecting the HMP8115 into a PC ISA slot for evaluation. It includes the HMP8115 NTSC/PAL decoder, 3MB of VRAM, and a NTSC/PAL encoder. The board accepts composite or S-video input and displays video on a standard TV. The ISA ...
Page 39
... ANTI-ALIAS FILTER 0.047 0.047 0 0 750 FIGURE 22. HMP8115 REFERENCE SCHEMATICS HMP8115 NTSC/PAL NTSC/PAL NTSC/PAL P15 P14 60 P13 ...
Page 40
... Input Logic Low Voltage Input Leakage Current Input Capacitance HMP8115 Thermal Information Thermal Resistance (Typical, See Note 42) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.5V Maximum Power Dissipation CC HMP8115CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W Maximum Storage Temperature Range . . . . . . . . . .-65 Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150 Maximum Lead Temperature (Soldering 10s 300 5.0V ...
Page 41
... SDA, SCL Rise Time SDA, SCL Fall Time ANALOG INPUT PERFORMANCE Composite Video Input Amplitude (Sync Tip to White Level) Luminance (Y) Video Input Amplitude (Sync Tip to White Level) Chrominance (C) Video Input Amplitude (Burst Amplitude) Video Input Impedance HMP8115 o = 5.0V (Continued SYMBOL TEST CONDITION V V ...
Page 42
... L OL 45. This should not be confused with Clock Jitter, since the HMP8115 does not generate the sample clock. Thus, clock jitter is solely depen- dent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from one scan line to the next. ...
Page 43
... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HMP8115 Q80.14x20 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYM- BOL ...