HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 12

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NOTES:
10. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and
NOTE:
16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT
In these output modes, DVALID may be configured to oper-
ate in one of four modes as controlled by the DVLD_LTC and
DVLD_DCYC bits of the GENLOCK CONTROL register
(04
DVLD_DCYC bit.
If DVLD_LTC=0 and DVLD_DCYC=0, DVALID is present
only during the active video time on active scan lines. Thus,
DVALID being asserted indicates valid pixel data is present
on the P0-P15 pixel outputs. DVALID is never asserted dur-
ing the blanking intervals. In this mode DVALID will have a
50% duty cycle only during the active video times. The tim-
ing diagrams for this mode can be found in Figures 12 and
13.
If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the
same as the first mode, with the exception that DVALID does
not have a 50% duty cycle. This mode is intended for back-
ward compatibility with HMP8112(A) timing dependencies in
9. Y
8. Y
BLANK
DVALID
DVALID
BLANK
P[15-8]
P[15-8]
H
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
be gated with the clock only during the blanking interval.
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
CLK
CLK
). Bit 4 is the DVLD_LTC bit and bit 5 is the
0
0
is the first active luminance pixel data of a line. Cb
is the first active luminance pixel data of a line. Cb
t
t
DVLD
DVLD
FIGURE 11. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
Cb
Cb
0
0
Y
Y
0
0
0
0
Cr
Cr
and Cr
and Cr
0
0
HMP8115
0
0
are first active chrominance pixel data in a line. Cb and Cr will alternate
are first active chrominance pixel data in a line. Cb and Cr will alternate
12
Y
Y
1
1
which DVALID did not have a 50% duty cycle timing and
other timing variations. The timing diagrams for this mode
can be found in Figures 14 and 15.
If DVLD_LTC=1 and DVLD_DCYC=0, DVALID is present the
entire line time on all scan lines. DVALID may occasionally
be negated for two consecutive CLK2 cycles just prior to
active video. In this mode DVALID is guaranteed have a 50%
duty cycle only during the active video times. The timing for
this mode differs from the timing shown in Figures 12 and 13
only in that DVALID will also be asserted during the blanking
portion of the video line time as described above.
If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present
during the entire line time on all scan lines. DVALID is
asserted during the blanking intervals as needed to ensure a
constant number of total samples per line. The timing for this
mode differs from the timing shown in Figures 14 and 15
only in that DVALID will also be asserted during the blanking
portion of the video line time as described above.
Cb
Cb
2
2
Y
Y
2
2
Cr
Cr
2
2
Y
Y
3
3
Cb
Cb
4
4
Y
4
Y
4