STE100A ST Microelectronics, Inc., STE100A Datasheet
STE100A
Related parts for STE100A
STE100A Summary of contents
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PCI 10/100 Ethernet controller with integrated PHY (3.3V) Features ■ IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant ■ Support for IEEE802.3x flow control ■ IEEE802.3u auto-negotiation support for 10BASE-T and 100BASE-TX ■ PCI bus interface rev. 2.2 compliant ■ ACPI and ...
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Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STE10/100A 4.4 Descriptors and buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 4.4.2 5 General EEPROM ...
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Overview 1 Overview 1.1 Block diagrams Figure 1. STE10/100A block diagram Flow control EMI Figure 2. STE10/100A system diagram PCI interface 4/82 Manchester encoder 4B/5B DMA Auto-negociation Tx FiFo 5B/4B Rx FiFo 100 clock recovery Serial EEPROM Boot ROM STE10/100A ...
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STE10/100A 1.2 Detailed features FIFO ● Provides independent transmission and receiving FIFOs, each 2k bytes long ● Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us ● Retransmits collided packet without reload from host memory ...
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Overview LED display ● Provides 2 LED display modes: – 3 LED displays for 100Mbps (on) or 10Mbps (off) link (remains on when link ok) or activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in ...
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STE10/100A 2 Pin description Figure 3. Pin connection Pin description 7/82 ...
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Pin description Table 1. Pin description Pin no. Name PCI bus interface 113 INTA# 114 RST# 116 PCI-CLK 117 GNT# 118 REQ# 119 PME# 120,121 AD-31,30 123,124 AD-29,28 126,127 AD-27,26 1,2 AD-25,24 6,7 AD-23,22 9,10 AD-21,20 12,13 AD-19,18 15,16 AD-17,16 ...
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STE10/100A Table 1. Pin description (continued) Pin no. Name 3 C-BEB3 17 C-BEB2 28 C-BEB1 42 C-BEB0 4 IDSEL 18 FRAME# 20 IRDY# 21 TRDY# 22 DEVSEL# 23 STOP# 24 PERR# 25 SERR# 26 PAR Boot ROM/EEPROM interface BrA0~3 56~59 ...
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Pin description Table 1. Pin description (continued) Pin no. Name Physical interface 107,109 TX+, TX- 105,104 RX+, RX- 101 Iref LED display & miscellaneous LED M1- LK/Act 90 or LED M2- Act LED M1- Speed 92 ...
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STE10/100A Table 1. Pin description (continued) Pin no. Name LED M1- Fd/Col 91 or LED M2- 10 link 89 Vaux-detect 88 Vcc-detect Digital power pins 5,11,19,31,36,39,45,51,55,75,93,112,115,125 8,14,27,38,40,48,60,85,111,122,128 Analog power pins 94,96,102,106,110 95,99,100,103,108 Type This pin can be programmed as mode ...
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Functional description 3 Functional description 3.1 Initialization flow Figure 4. STE10/100A initialization flow Search NIC Get base IO address Get IRQ value Reset MAC (CSR0) Reset PHY (XR0) Read EEPROM from CSR9 Set physical address (CSR25, 26) Prepare transmit descriptor ...
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STE10/100A 3.2 Network packet buffer management 3.2.1 Descriptor structure types During normal network transmit operations, the STE10/100A transfers the data packets from transmit buffers in the host’s memory to the STE10/100A’s transmit FIFO. For receive operations, the STE10/100A transfers the ...
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Functional description Chain structure There is only one buffer per descriptor in chain structure. Figure 6. Frame buffer chain structure CSR3 or CSR4 Descriptor pointer 14/82 Descriptor own --- Length 1 Data buffer Buffer1 pointer Next pointer own --- Length ...
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STE10/100A 3.2.2 Descriptor management OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access Transmit descriptors Figure 7. Transmit descriptor management Ext packet to be transmitted Ext packet to be transmitted Own ...
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Functional description Receive descriptors Figure 8. Receive descriptor management Own bit = 1 Own bit = 1 Next descriptor ready Next descriptor ready for incoming packet for incoming packet Filled descriptor pointer Filled descriptor pointer 16/ Packet 2 ...
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STE10/100A 3.3 Transmit scheme and transmit early interrupt 3.3.1 Transmit scheme Figure 9. Transmit scheme Own = 0 Own = 0 Exit Exit Back-off Back-off Initialize descriptor Initialize descriptor Place data in host memory Place data in host memory Set ...
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Functional description 3.3.2 Transmit pre-fetch data flow – Transmit FIFO size=2K-byte – Two packets in the FIFO at the same time – Meet the transmit min. back-to-back Figure 10. Transmit pre-fetch data flow Place the 1st packet data into host ...
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STE10/100A 3.4 Receive scheme and receive early interrupt scheme The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt) Incoming packet Receive FIFO ...
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Functional description 3.5 Network operation 3.5.1 MAC operation The MAC (Media access control) portion of STE10/100A incorporates the essential protocol requirements for operating as an IEEE802.3 and ethernet compliant node. Format Table 2. Format Field Preamble Start frame diameter Destination ...
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STE10/100A Collision handling The scheduling of re-transmissions are determined by a controlled randomization process called “truncated binary exponential back-off”. At the end of enforcing a collision (jamming), the STE10/100A delays before attempting to re-transmit the packet. The delay is an ...
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Functional description End-of-stream delimiter-ESD (/T/R/) In order to indicate the termination of normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of the FCS. Scrambling All the encoded data (including the idle, SSD, ...
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STE10/100A Data conversions of NRZI to NRZ and serial to parallel After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel ...
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Functional description Full duplex and half duplex operation of transceiver The transceiver can operate in either full duplex or half duplex network applications. In full duplex, both transmission and reception can take place simultaneously. In full duplex mode, collision (COL) ...
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STE10/100A 3.5.3 Flow control in full duplex application The PAUSE function is used to inhibit transmission of data frames for a specified period of time. The STE10/100A supports the full duplex protocol of IEEE802.3x. To support the PAUSE function, the ...
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Functional description Receive operation for PAUSE function Upon reception of a valid MAC Control frame, the STE10/100A will start a timer for the length of time specified by the MAC control parameters field. When the timer value reaches zero, the ...
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STE10/100A 3.6 LED display operation The STE10/100A provides 2 LED display modes; the detailed descriptions of their operation are described in the pin description section. First mode – 3 LED displays – 100Mbps (on) or 10Mbps (off) – Link (Remains ...
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Functional description 3.8 Wake on LAN function The STE10/100A can assert a signal to wake up the system when it has received a Magic Packet from the network. The wake on LAN operation is described as follow. The Magic Packet ...
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STE10/100A D3 (Software visible D3) hot When the STE10/100A is brought back to D0 from D3hot the software must perform a full initialization. The STE10/100A in the D3hot state responds to configuration cycles as long as power and clock are ...
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Registers and descriptors description 4 Registers and descriptors description Note: There are three kinds of registers within the STE10/100A: STE10/100A configuration registers, PCI control/status registers, and transceiver control/status registers. The STE10/100A configuration registers are used to initialize and configure the ...
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STE10/100A Table 5. STE10/100A configuration registers table offset b31 00h 04h Base class 08h 0ch 10h 14h 18h~28h 2ch 30h 34h 38h 3ch Max_Lat 40h Reserved 80h c0h c4h 1. Automatically recalled from EEPROM when PCI reset is deserted DS(40h), ...
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Registers and descriptors description 4.1.1 STE10/100A configuration registers description Table 6. Configuration registers description Bit # Name CR0 (offset = 00h), LID - Loaded identification number of device and vendor 31~16 LDID 15~0 LVID From EEPROM: Loaded from EEPROM CR1 ...
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STE10/100A Table 6. Configuration registers description (continued) Bit # Name 20 NC 19~ 9 --- 8 CSE 7 --- 6 CPE 5~ 3 --- 2 CMO 1 CMSA 0 CIOSA R/W: Read and write able. RO: Read able only. CR2 ...
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Registers and descriptors description Table 6. Configuration registers description (continued) Bit # Name CR3 (offset = 0ch Latency timer 31~16 --- 15 CLS CR4 (offset = 10h), IOBA - I/O base address 31~ ...
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STE10/100A Table 6. Configuration registers description (continued) Bit # Name 31~10 BRBA --- 0 BRE CR13 (offset = 34h Capabilities pointer 31~8 --- 7~0 CP CR15 (offset = 3ch Configuration interrupt 31~24 ML ...
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Registers and descriptors description Table 6. Configuration registers description (continued) Bit # Name 31~16 DID 15~0 VID CR48 (offset = c0h), PMR0, Power management register 0 31 PSD3c, 30 PSD3h, 29 PSD2, 28 PSD1, 27 PSD0 26 D2S 25 D1S ...
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STE10/100A Table 6. Configuration registers description (continued) Bit # Name 7~0 CAPID CR49 (offset = c4h), PMR1, Power management register 1 31~16 --- 15 PMEST 14,13 DSCAL 12~9 DSEL 8 PME_En Registers and descriptors description Description Capability identifier. This value ...
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Registers and descriptors description Table 6. Configuration registers description (continued) Bit # Name 7~2 --- 1,0 PWRS 1. R/W1C: Read only and write one cleared 38/82 Description Reserved PowerState. This two bit field is used both to determine the current ...
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STE10/100A 4.2 PCI control/status registers Table 7. PCI control/status registers list Offset from base address of CSR 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h 68h 70h 78h 80h 84h 88h 8ch 90h 94h 98h ...
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Registers and descriptors description Table 8. Control/status register description Bit # Name CSR0 (offset = 00h), PAR - PCI access register 31~25 --- 24 MWIE 23 MRLE 22 --- 21 MRME 20~19 --- 18,17 TAP 16 --- 15, 14 CAL ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 7 BLE DSL 1 BAR 0 SWR R/W* = Before writing the transmit and receive operations should be stopped. CSR1 (offset = 08h), TDR - Transmit demand ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name CSR5 (offset = 28h Status register 31~ 26 ---- 25~ 23 BET 22 19~ NISS 42/82 Description Reserved Bus error type. ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 15 AISS 14 ---- 13 FBE 12 --- 11 GPTT 10 --- 9 RWT 8 RPS 7 RDU 6 RCI 5 TUF Registers and descriptors description Description Abnormal interrupt status ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 4 --- 3 TJT 2 TDU 1 TPS 0 TCI LH = High Latching and cleared by writing 1. CSR6 (offset = 30h), NAR - Network access ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name --- SBC 4 --- --- --- W* = only write when the ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name CSR7 (offset = 38h), IER - Interrupt enable register 31~17 --- 16 NIE 15 AIE 14 --- 13 FBEIE 12 --- 11 GPTIE 10 --- 9 RWTIE ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 2 TDUIE 1 TPSIE 0 TCIE CSR8 (offset = 40h), LPC - Lost packet counter 31~17 --- 16 LPCO 15~0 LPC CSR9 (offset = 48h), SPR - Serial port register ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 1 SCLK 0 SCS CSR11 (offset = 58h), TMR - General - Purpose timer 31~17 --- 16 COM 15~0 GTV CSR13 (offset = 68h), WCSR – Wake-up ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 9 MPRE 8 LSCE 7-3 --- 2 WFR 1 MPR 0 LSC R/W1C*, Read only and write one cleared. CSR14 (offset = 70h), WPDR – Wake-up pattern data register Offset ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 0024h 0028h 002ch 0030h 0034h 0038h 003ch 0040h 0044h 0048h 004ch 0050h 0054h 0058h 005ch 0060h Offset value is from 0-255 (8-bit width). To load the whole ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 2 JCLK JBD CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2) 31 TEIS 30 REIS 29 XIS 28 TDIS 27 --- 26 PFR 25~ ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 22 19~ ANISS 15 AAISS 14~0 LH* = High Latching and cleared by writing 1 CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name 16 ANISE 15 AAIE 14~0 CSR18 (offset = 88h Command register bit31 to bit16 automatically recall from EEPROM 31 D3CS 30-28 AUXCL 27-24 --- 4LEDmod 23 e_on 22, ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name WOL 17~7 --- 6 RWP 5 PAUSE 4 RTE 3~2 DRT 1 SINT 0 ATUR 54/82 Description Power management. Enables the STE10/100A power management ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name CSR19 (offset = 8ch), PCIC - PCI bus performance counter 31~16 CLKCNT 15~8 --- 7~0 DWCNT RO* = Read only and cleared by reading. CSR20 (offset = 90h), PMCSR - ...
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Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 1,0 PWRS CSR23 (offset = 9ch), TXBR - Transmit burst count / time-out 31~21 --- 20~16 TBCNT 15~12 --- 11~0 TTO CSR24 (offset = a0h), FROM - ...
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STE10/100A Table 8. Control/status register description (continued) Bit # Name CSR25 (offset = a4h), PAR0 - Physical address register 0 automatically recalled from EEPROM 31~24 PAB3 23~16 PAB2 15~8 PAB1 7~0 PAB0 CSR26 (offset = a8h), PAR1 - Physical address ...
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Registers and descriptors description 4.3 Transceiver(XCVR) registers There are 11 16-bit registers supporting the transceiver portion of STE10/100A, including 7 basic registers defined according to clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28 “Physical Layer link signaling ...
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STE10/100A Table 10. Transceiver registers description Bit # Name XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below. 15 XRST 14 XLBEN 13 SPSEL 12 ANEN 11 PDEN 10 --- 9 RSAN 8 ...
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Registers and descriptors description Table 10. Transceiver registers description (continued) Bit # Name 12 10FD 11 10HD 10~6 --- 5 ANC LINK 1 JAB 0 EXT LL* = Latching Low and clear by read. LH* ...
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STE10/100A Table 10. Transceiver registers description (continued) Bit # Name XR4(offset = c4h) - ANA, Auto-negotiation advertisement 15 NXTPG 14 --- 13 RF 12,11 --- TXF 7 TXH 6 10F 5 10H 4~0 SF XR5(offset ...
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Registers and descriptors description Table 10. Transceiver registers description (continued) Bit # Name 9 LPT4 8 LPTXF 7 LPTXH 6 LP10F 5 LP10H 4~0 LPSF XR6(offset = cch) - ANE, auto-negotiation expansion 15~5 --- 4 PDF 3 LPNP 2 NP ...
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STE10/100A Table 10. Transceiver registers description (continued) Bit # Name XR7(offset = d0h) - XMC, XCVR mode control 15~12 --- 11 LD 10~0 --- XR8(offset = d4h) - XCIIS, XCVR configuration information and interrupt status 15~10 ---- 9 SPEED 8 ...
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Registers and descriptors description Table 10. Transceiver registers description (continued) Bit # Name 0 REF LH = High Latching and cleared by reading. XR9(offset = d8h) - XIE, XCVR interrupt enable register 15~7 --- 6 ANCE 5 RFE 4 LDE ...
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STE10/100A Table 10. Transceiver registers description (continued) Bit # Name 11, 10 --- 9 ENRLB 8 ENDCR 7 ENRZI 6 --- 5 ISOTX 4~2 CMODE 1 DISMLT 0 DISCRM Registers and descriptors description Description Reserved Enable remote loop-back function. 1: ...
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Registers and descriptors description 4.4 Descriptors and buffer management The STE10/100A provides receive and transmit descriptors for packet buffering and management. 4.4.1 Receive descriptor Table 11. Receive descriptor table 31 RDES0 Own RDES1 RDSE2 RDSE3 Note: Descriptors and receive buffers ...
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STE10/100A Table 12. Receive descriptor description (continued) Bit# Name reserved Default = RDES1 31~26 --- 25 RER 24 RCH 23~22 ...
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Registers and descriptors description 4.4.2 Transmit descriptor Table 13. Receive descriptor table 31 TDES0 Own TDES1 TDSE2 TDSE3 Table 14. Transmit descriptor description Bit# Name TDSE0 31 OWN 30-24 --- 23-22 UR 21-16 --- 13-12 ----- ...
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STE10/100A Table 14. Transmit descriptor description (continued) Bit# Name 29 FS 28,27 --- TER 24 TCH 23 DPD 22 --- 21-11 TBS2 10-0 TBS1 TDES2 31~0 BA1 TDES3 31~0 BA2 Registers and descriptors description Description First descriptor ...
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General EEPROM format description 5 General EEPROM format description Table 15. Connection type definition Offset Length ...
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STE10/100A Table 16. Connection type definition Name 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 General EEPROM format description Description Software driver default Auto-negotiation Power-on auto-detection Auto sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT ...
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Electrical specifications and timings 6 Electrical specifications and timings Table 17. Absolute maximum ratings Supply voltage(Vcc) Input voltage Output voltage Storage temperature Ambient temperature ESD protection Table 18. General DC specifications Symbol General DC Vcc Supply voltage Icc Power supply ...
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STE10/100A Table 18. General DC specifications (continued) Symbol 10BASE-T voltage/current characteristics Input differential accept peak Vida10 voltage Input differential reject peak Vidr10 voltage Output differential peak Vod10 voltage 100BASE-TX voltage/current Characteristics Input differential accept peak Vida100 voltage Input differential reject ...
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Electrical specifications and timings Figure 16. PCI clock waveform Table 21. X1 specifications Symbol TX1d X1 duty cycle TX1p X1 period TX1t X1 tolerance TX1C X1 load capacitance L Table 22. PCI timing Symbol Clock to signal valid delay Tval ...
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STE10/100A Figure 17. PCI timings INPUT Table 23. Flash interface timings Symbol Tfcyc Read/write cycle time Address to read data setup Tfce time Tfce CS# to read data setup time OE# active to read data Tfoe setup time OE# inactive ...
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Electrical specifications and timings Figure 18. Flash write timings ADDRESS Figure 19. Flash read timings ADDRESS Table 24. EEPROM Interface Timings Symbol Tscf Serial clock frequency Delay from CS high to SK Tecss high Tecsh Delay from SK low to ...
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STE10/100A Figure 20. Serial EEPROM timings CS CLK DI Table 25. 10BASE-T normal link pulse (NLP) timings specifications Symbol Tnpw NLP width Tnpc NLP period Figure 21. Normal link pulse timings Table 26. Auto-negotiation fast link pulse (FLP) timings specifications ...
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Electrical specifications and timings Figure 22. Fast link pulse timings Table 27. 100BASE-TX transmitter AC timings specification Symbol TDP-TDN differential output Tjit peak jitter 78/82 Tflcpp Tflcpd Tflpw Tflbp Tflbw Parameter Test condition STE10/100A Min. Typ. Max. Units 1.4 ps ...
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STE10/100A 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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Package mechanical data Figure 23. Package mechanical data mm DIM. MIN. TYP. A 3.04 A1 0.25 0.33 A2 2.57 2.71 b 0. 0.5 HD 23.2 HE 17.2 L 0.73 0.88 L1 1.60 ZD ...
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STE10/100A 8 Ordering information Table 28. Order codes Part number E-STE10/100A 9 Revision history Table 29. Document revision history Date 06-Nov-2002 28-Feb-2007 PQFP128 (14mm x 20mm x 2.7mm) Revision 7 Previous release (as revision A07) Removed the STE10/100E order code ...
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