STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 30

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
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Note:
4.1
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Registers and descriptors description
There are three kinds of registers within the STE10/100A: STE10/100A configuration
registers, PCI control/status registers, and transceiver control/status registers.
The STE10/100A configuration registers are used to initialize and configure the
STE10/100A and for identifying and querying the STE10/100A.
The PCI control/status registers are used to communicate between the host and
STE10/100A. The host can initialize, control, and read the status of the STE10/100A
through mapped I/O or memory address space.
The STE10/100A contains 11 16-bit registers to supported transceiver control and status.
They include 7 basic registers which are defined according to clause 22 “Reconciliation
Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for
10 Mb/s and 100 Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In
addition, 4 special registers are provided for advanced chip control and status.
The STE10/100A also provides receive and transmit descriptors for packet buffering and
management.
STE10/100A configuration registers
An STE10/100A software driver can initialize and configure the chip by writing its
configuration registers. The contents of configuration registers are set to their default values
upon power-up or whenever a hardware reset occurs, but their settings remain unchanged
whenever a software reset occurs. The configuration registers are byte, word, and double
word accessible.
Table 4.
Offset
00h
04h
08h
10h
14h
30h
34h
40h
80h
0ch
2ch
3ch
c0h
c4h
STE10/100A configuration registers list
Index
CR11
CR12
CR13
CR15
CR16
CR32
CR48
CR49
CR0
CR1
CR2
CR3
CR4
CR5
Name
BRBA
PMR0
PMR1
IOBA
CINT
CSC
MBA
SIG
SID
LID
CC
CP
DS
LT
Loaded device ID and vendor ID
Configuration status and command
Class code and revision number
Latency timer
IO base address
Memory base address
Subsystem ID and vendor ID
Boot ROM base address (ROM size = 128Kbit)
Capability pointer
Configuration interrupt
Driver space for special purpose
Signature of STE10/100A
Power management register 0
Power management register 1
Description
STE10/100A