STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 37

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 6.
CR49 (offset = c4h), PMR1, Power management register 1
31~16
14,13
12~9
Bit #
7~0
15
8
PME_En
PMEST
DSCAL
CAPID
Configuration registers description (continued)
Name
DSEL
---
Capability identifier. This value is always 01h,
indicating the link list item as being the PCI power
management registers.
Reserved
PME_Status. This bit is set whenever the
STE10/100A detects a wake-up event, regardless of
the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the
STE10/100A to deassert PME# (if so enabled).
Writing a “0” has no effect.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not
support PME# generation from D3cold), this bit is by
default 0; otherwise, PMEST is cleared upon power-
up reset only and is not modified by either hardware
or software reset.
Data_Scale. Indicates the scaling factor to be used
when interpreting the value of the data register. This
field is required for any function that implements the
data register.
The STE10/100A does not support data register and
Data_Scale.
Data_Select. This four bit field is used to select
which data is to be reported through the data
register and Data_Scale field. This field is required
for any function that implements the data register.
The STE10/100A does not support Data_select.
PME_En. When set, enables the STE10/100A to
assert PME#. When cleared, disables the PME#
assertion.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not
support PME# generation from D3cold), this bit is by
default 0; otherwise, PME_En is cleared upon power
up reset only and is not modified by either hardware
or software reset.
Description
Registers and descriptors description
Default
0000b
01h
00b
X
X
R/W1C
RW type
R/W
R/W
RO
RO
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