STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 18

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Functional description
3.3.2
3.3.3
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Transmit pre-fetch data flow
Figure 10. Transmit pre-fetch data flow
Transmit early interrupt scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
FIFO-to-host memory operation (2nd packet)
Driver return buffer to upper layer
Driver return buffer to upper layer
FIFO-to-host memory operation (3rd packet)
Host to TX-FIFO memory
Host to TX-FIFO memory
operation
operation
Transmit data from FIFO to media
Transmit data from FIFO to media
Normal interrupt after transmit
Normal interrupt after transmit
completed
completed
Driver return buffer to upper layer
Driver return buffer to upper layer
Early interrupt after host to TX-
Early interrupt after host to TX-
FIFO operation completed
FIFO operation completed
FIFO-to-host memory operation (1st packet)
Place the 2nd packet data into host memory
Place the 3rd packet data into host memory
Place the 1st packet data into host memory
–
–
–
Transmit FIFO size=2K-byte
Two packets in the FIFO at the same time
Meet the transmit min. back-to-back
Issue transmit demand
Transmit enable
Check point
Check point
Time
Time
Time
: handled by driver
: handled by driver
: handled by driver
Transmit
threshold
1st packet
Check the
next packet
The saved time when transmit
The saved time when transmit
early interrupt is implemented
early interrupt is implemented
IFG
1st packet is
transmitted, check
the 3rd packet
: handled by STE10/100A
: handled by STE10/100A
: handled by STE10/100A
2nd packet
STE10/100A
PC00356
PC00355