STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 43

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 8.
Bit #
15
14
13
12
11
10
9
8
7
6
5
Control/status register description (continued)
Name
GPTT
AISS
RWT
RDU
RPS
FBE
TUF
RCI
----
---
---
Abnormal interrupt status summary. Set if any of
the following bits of CSR5 are asserted:
Reserved
Fatal bus error.
1: on occurrence of parity error, master abort, or
target abort (see bits 25~23 of CSR5). The
STE10/100A will disable all bus access. A
software reset is required to recover from a
parity error.
Reserved
General purpose timer timeout, based on
CSR11 timer register
Reserved
Receive watchdog timeout, based on CSR15
watchdog timer register
Receive process stopped, receive state = stop
Receive descriptor unavailable.
1: when the next receive descriptor can not be
obtained by the STE10/100A. The receive
process is suspended in this situation. To restart
the receive process, the ownership bit of the next
receive descriptor should be set to STE10/100A
and a receive poll demand command should be
issued (if the receive poll demand is not issued,
the receive process will resume when a new
recognized frame is received).
Receive completed interrupt.
1: when a frame reception is completed.
Transmit under-flow.
1: when an under-flow condition occurs in the
transmit FIFO during transmitting. The transmit
process will enter the suspended state and
report the under-flow error on bit 1 of TDES0.
–
–
–
–
–
–
–
–
TPS, transmit process stopped (bit 1)
TJT, transmit jabber timer time-out (bit
3)
TUF, transmit under-flow (bit 5)
RDU, receive descriptor unavailable
(bit 7)
RPS, receive process stopped (bit 8)
RWT, receive watchdog time-out (bit
9)
GPTT, general purpose timer time-out
(bit 11)
FBE, fatal bus error (bit 13)
Description
Registers and descriptors description
Default
0
0
0
0
0
0
0
0
RW type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
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