AD9882 Analog Devices, AD9882 Datasheet
AD9882
Manufacturer Part Number
AD9882
Description
Dual Interface for Flat Panel Displays
Manufacturer
Analog Devices
Datasheet
1.AD9882.pdf
(36 pages)
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GENERAL DESCRIPTION
The AD9882 offers designers the flexibility of an analog interface
and Digital Visual Interface (DVI) receiver integrated on a single
chip. Also included is support for High bandwidth Digital
Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 ¥ 1024 at 75 Hz).
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and Hsync. Three-
state CMOS outputs may be powered from 2.2 V to 3.3 V.
The AD9882’s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882
also offers full sync processing for composite sync and Sync-on-
Green (SOG) applications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FEATURES
Analog Interface
Digital Interface
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converter
Microdisplays
Digital TV
140 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
DVI 1.0 Compatible Interface
112 MHz Operation
High Skew Tolerance of 1 Full Input Clock
Sync Detect for “Hot Plugging”
Supports High Bandwidth Digital Content Protection
Digital Interface
The AD9882 contains a DVI 1.0 compatible receiver and supports
display resolutions up to SXGA (1280 ¥ 1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
clock cycle.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9882 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
the HDCP v1.0 protocol.
Fabricated in an advanced CMOS process, the AD9882 is
provided in a space-saving 100-lead LQFP surface-mount plastic
package and is specified over the 0∞C to 70∞C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DDCSDA
DDCSCL
HSYNC
VSYNC
SOGIN
R
R
R
TERM
R
R
R
MDA
R
G
B
R
R
R
MCL
FILT
SCL
SDA
XC+
XC–
X0+
X0–
X1+
X1–
X2+
X2–
AIN
AIN
AIN
A
0
ANALOG INTERFACE
AD9882
DIGITAL INTERFACE
CLAMP
CLAMP
CLAMP
SERIAL REGISTER AND
FUNCTIONAL BLOCK DIAGRAM
POWER MANAGEMENT
RECEIVER
PROCESSING AND
HDCP
GENERATION
DVI
CLOCK
SYNC
© 2003 Analog Devices, Inc. All rights reserved.
8
8
8
Flat Panel Displays
A/D
A/D
A/D
Dual Interface for
SOGOUT
8
8
8
DATACK
DATACK
HSOUT
VSOUT
HSYNC
VSYNC
REF
G
G
R
B
R
B
OUT
OUT
OUT
OUT
OUT
OUT
DE
MUXES
AD9882
www.analog.com
8
8
8
R
G
B
DATACK
HSOUT
VSOUT
SOGOUT
DE
REFBYPASS
OUT
OUT
OUT
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