AD9882 Analog Devices, AD9882 Datasheet - Page 16

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table VII.
Four programmable registers are provided to optimize the
performance of the PLL. These registers are:
1. The 12-bit Divisor Register (Registers 01H and 02H). The
2. The 2-bit VCO Range Register (Register 03H, Bits 6 and 7).
input Hsync frequencies range from 15 kHz to 110 kHz. The
PLL multiplies the frequency of the Hsync signal, producing
pixel clock frequencies in the range of 12 MHz to 140 MHz.
The Divisor Register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)
To improve the noise performance of the AD9882, the VCO
operating frequency range is divided into three overlapping
regions. The VCO Range register sets this operating range.
The frequency ranges for the lowest and highest regions are
shown in Table V.
Standard
VGA
SVGA
XGA
SXGA
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Figure 6. PLL Loop Filter Detail
Refresh
Resolution
640 ¥ 480
800 ¥ 600
1024 ¥ 768
1280 ¥ 1024
0.0082 F
C
P
FILT
R
2.74k
C
0.082 F
Z
Z
Rate (Hz)
Horizontal
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
P
VD
Frequency (kHz)
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
–16–
3. The 3-bit Charge Pump Current Register (Register 03H,
4. The 5-bit Phase Adjust Register (Register 04H, Bits 3–7).
Bits 3–5). This register allows the current that drives the
low-pass loop filter to be varied. The possible current values
are listed in Table VI.
The phase of the generated sampling clock may be shifted to
locate an optimum sampling point within a clock cycle. The
Phase Adjust Register provides 32 phase-shift steps of 11.25∞
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin.
PV1
0
0
1
Pixel Rate (MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
Table VI. Charge Pump Current/Control Bits
Ip2
0
0
0
0
1
1
1
1
Table V. VCO Frequency Ranges
PV0
0
1
0
Ip1
0
0
1
1
0
0
1
1
Ip0
0
1
0
1
0
1
0
1
Pixel Clock Range (MHz)
12–41
41–82
82–140
VCORNGE
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
11
Current (
50
100
150
250
350
500
750
1500
m
CURRENT
101
101
101
110
101
110
101
101
101
101
110
110
101
101
101
110
A)
REV. A