AD9882 Analog Devices, AD9882 Datasheet - Page 28

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
11
A bit that determines whether the GREEN channel is clamped
to ground or to midscale.
Clamp
0
1
The default setting for this register is 0.
11
A bit that determines whether the BLUE channel is clamped to
ground or to midscale.
Clamp
0
1
The default setting for this register is 0.
11
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin or
the output from the sync separator needs to be made (Register
10H, Bits 1, 0). To disable coast, the user must set Register 11H,
Bit 2 to 1 and 11H, Bit 1 to 1.
Select
0
1
The default for this register is 1.
11
This register is used to override the internal circuitry that deter-
mines the polarity of the coast signal going into the PLL. When
disabling coast, Register 11, Bit 2 must be set to 1 and Register
11H, Bit 1 must be set to 1. This register only works when Coast
is disabled. It does not work with internal Coast.
Override Bit
0
1
The default for coast polarity override is 0.
11
A bit to indicate the polarity of the coast signal that is applied to
the PLL coast input.
This register can only be used when coast is disabled and
Register 11H, Bit 2 is set to 1.
CSTPOL
0
1
The power-up default value is CSTPOL = 1.
Table XXVII. Coast Input Polarity Override Settings
3
2
1
5
4
Table XXIV. GREEN Clamp Select Settings
Table XXVIII. Coast Input Polarity Settings
Table XXV. BLUE Clamp Select Settings
Coast Select
Coast Input Polarity Override
Coast Input Polarity
Table XXVI. Coast Enable Settings
Function
Clamp to ground
Clamp to midscale (Pin 74)
Function
Clamp to ground
Clamp to midscale (Pin 74)
Result
Coast disabled
Internally generated coast signal
Function
Active LOW
Active HIGH
GREEN Clamp Select
BLUE Clamp Select
Result
Coast polarity determined by chip
Coast polarity determined by user
–28–
12
This register allows the coast signal to be applied prior to the
Vsync signal. This is necessary in cases where pre-equalization
pulses are present. This register defines the number of edges
that will be filtered before Vsync on a composite sync.
The default is 0.
13
This register allows the coast signal to be applied following the
Vsync signal. This is necessary in cases where post-equalization
pulses are present. The step size for this control is one Hsync
period. This register defines the number of edges that will be
filtered after Vsync on a composite sync.
The default is 0.
14
The two bits select the drive strength for the high speed digital
outputs (all data output and clock output pins). Higher drive
strength results in faster rise/fall times, and in general makes it
easier to capture data. Lower drive strength results in slower
rise/fall times and helps reduce EMI and digitally generated
power supply noise.
Bit 7
1
0
0
The default for this register is 11, high drive strength. (This option works on
both the analog and digital interfaces.)
14
Bits that select the analog bandwidth.
Bit 5
0
1
14
A control bit for the inversion of the output data clock (Pin 85).
This function works only for the digital interface. When not
inverted, data is output on the falling edge of the data clock.
See the timing diagrams, Figures 14 and 15, to see how this
affects timing.
Clk Inv
0
1
The default for this register is 0 (not inverted).
7–0
7–0
7–6
5
4
Table XXIX. Output Drive Strength Settings
Table XXXI. Clock Output Invert Settings
Table XXX. Analog Bandwidth Control
Pre-Coast
Post-Coast
Output Drive
Programmable Analog Bandwidth
Clk Inv
Analog Bandwidth
10 MHz
300 MHz
Function
Not inverted
Inverted
Bit 6
X
1
0
Data Output Clock Invert
Result
High drive strength
Medium drive strength
Low drive strength
REV. A