AD9882 Analog Devices, AD9882 Datasheet - Page 26

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
HSYNC OUTPUT PULSEWIDTH
07
An 8-bit register that sets the duration of the Hsync output pulse.
The leading edge of the Hsync output is triggered by the internally
generated, phase adjusted PLL feedback clock. The AD9882
then counts a number of pixel clocks equal to the value in this
register minus one. This triggers the trailing edge of the Hsync
output, which is also phase adjusted.
INPUT GAIN
08
An 8-bit word that sets the gain of the RED channel. The AD9882
can accommodate input signals with a full-scale range of between
0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to
an input range of 1.0 V. A REDGAIN of 0 establishes an input
range of 0.5 V. Note that INCREASING REDGAIN results in
the picture having LESS CONTRAST (the input signal uses
fewer of the available converter codes). See Figure 2.
09
An 8-bit word that sets the gain of the GREEN channel. See
REDGAIN (08).
0A
An 8-bit word that sets the gain of the BLUE channel. See
REDGAIN (08).
INPUT OFFSET
0B
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately one
LSB change in the ADC offset. Therefore, the absolute magni-
tude of the offset adjustment scales as the gain of the channel is
changed. A nominal setting of 64 results in the channel nominally
clamping the back porch (during the clamping interval) to code 00.
An offset setting of 127 results in the channel clamping to code
63 of the ADC. An offset setting of 0 clamps to code –64 (off the
bottom of the range). Increasing the value of RED offset
DECREASES the brightness of the channel.
0C
A 7-bit offset binary word that sets the dc offset of the GREEN
channel. See REDOFST (0B).
0D
A 7-bit offset binary word that sets the dc offset of the BLUE
channel. See REDOFST (0B).
0E
This register is used to set the responsiveness of the sync separator.
It sets how many internal 5 MHz clock periods the sync separa-
tor must count to before toggling high or low. It works like a
low-pass filter to ignore Hsync pulses in order to extract the
Vsync signal. This register should be set to some number greater
than the maximum Hsync pulsewidth. Note: the sync separator
threshold uses an internal dedicated clock with a frequency of
approximately 5 MHz.
The default for this register is 20H.
7–0
7–0
7–0
7–0
7–1
7–1
7–1
7–0
Hsync Output Pulsewidth
REDGAIN
GREENGAIN GREEN Gain
BLUEGAIN
RED Channel Offset Adjust
GREEN Channel Offset Adjust
BLUE Channel Offset Adjust
Sync Separator Threshold
RED Gain
BLUE Gain
–26–
0F
This register allows the comparator threshold of the Sync-on-Green
slicer to be adjusted. This register adjusts it in steps of 10 mV,
with the minimum setting equaling 10 mV and the maximum
setting equaling 330 mV.
The default setting is 15 decimal and corresponds to a threshold
value of 170 mV.
0F
This bit is used to override the automatic interface selection
(Bit 3 in Register 15H). To override, set this bit to logic 1. When
overriding, the active interface is set via Bit 1 in this register.
AIO
0
1
The default for this register is 0.
0F
This bit is used under two conditions. It is used to select the active
interface when the override bit is set (Register 0FH, Bit 2).
Alternatively, it is used to determine the active interface when
not overriding but both interfaces are detected.
AIS
0
1
The default for this register is 0.
10
This register is used to override the internal circuitry that determines
the polarity of the Hsync signal going into the PLL.
Override Bit
0
1
The default for Hsync polarity override is 0. (Polarity determined by chip.)
10
A bit that must be set to indicate the polarity of the Hsync signal
that is applied to the PLL Hsync input.
HSPOL
0
1
Active LOW means the leading edge of the Hsync pulse is negative-
going. All timing is based on the leading edge of Hsync, which
is the FALLING edge. The rising edge has no effect.
Table XIV. Hsync Input Polarity Override Settings
7–3
2
1
7
6
Table XII. Active Interface Override Settings
Result
Autodetermine the active interface.
Override, Bit 1 determines the active interface.
Result
Analog interface
Digital interface
Table XIII. Active Interface Select Settings
Table XV. Hsync Input Polarity Settings
Sync-on-Green Slicer Threshold
AIO
AIS
Hsync Input Polarity Override
HSPOL
Function
Active LOW
Active HIGH
Result
Hsync polarity determined by chip.
Hsync polarity determined by Register 10H,
Bit 6.
Active Interface Override
Active Interface Select
Hsync Input Polarity
REV. A