AD9882 Analog Devices, AD9882 Datasheet - Page 34

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
THEORY OF OPERATION
Sync Stripper
This section is devoted to the basic operation of the sync pro-
cessing engine. (Refer to Figure 18.)
The purpose of the sync stripper is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems; only those with Sync-on-Green. The sync signal
is extracted from the GREEN channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a variable trigger level, nominally 0.15 V above the clamped
level. The output signal is typically a composite sync signal
containing both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite sync
signal. It does this through a low-pass filter-like or integrator-
like operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal. So, it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9882 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the polarity
of the composite sync signal. (Polarities are determined elsewhere
on the chip.) The basic idea is that the counter counts up when
Hsync pulses are present. But since Hsync pulses are relatively
short in width, the counter only reaches a value of N before the
pulse ends. It then starts counting down, eventually reaching
0 before the next Hsync pulse arrives. The specific value of N will
vary for different video modes, but will always be less than 255.
For example, with a 1 ms width Hsync, the counter will only reach
5 (1 ms/200 ns = 5). Now, when Vsync is present on the composite
sync the counter will also count up. However, since the Vsync
signal is much longer, it will count to a higher number M. For
most video modes, M will be at least 255. So, Vsync can be detected
on the composite sync signal by detecting when the counter
counts to higher than N. The specific count that triggers detection
(T) can be programmed through the serial register (0EH).
Once Vsync has been detected, a similar process detects when
it goes inactive. At detection, the counter first resets to 0, then
starts counting up when Vsync goes away. In a way similar to
the previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is determined
to be absent, the counter resets to 0 and begins the cycle again.
PCB LAYOUT RECOMMENDATIONS
The AD9882 is a high precision, high speed analog device. In
order to derive the maximum performance out of the part, it is
important to have a well laid out board. The following is a guide
for designing a board using the AD9882.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9882 as close as possible to the
graphics VGA connector. Long input trace lengths are undesirable
because they will pick up more noise from the board and other
external sources.
–34–
Place the 75 W termination resistors (see Figure 1) as close to the
AD9882 chip as possible. Any additional trace length between the
termination resistors and the input of the AD9882 increases the
magnitude of reflections, which will corrupt the graphics signal.
Use 75 W matched impedance traces. Trace impedances other
than 75 W will also increase the chance of reflections.
The AD9882 has a very high input bandwidth (300 MHz). While
this is desirable for acquiring a high resolution PC graphics signal
with fast edges, it means that it will also capture any high frequency
noise present. Therefore, it is important to reduce the amount
of noise that gets coupled to the inputs. Avoid running any
digital traces near the analog inputs.
Due to the high bandwidth of the AD9882, sometimes low-pass
filtering the analog inputs can help to reduce noise. (For many
applications, filtering is unnecessary.) Experiments have shown
that placing a series ferrite bead prior to the 75 W termination
resistor is helpful in filtering out excess noise. Specifically, the
part used was the #2508051217Z0 from Fair-Rite, but different
applications may work best with different bead values. Alternatively,
placing a 100 W to 120 W resistor between the 75 W termination
resistor and the input coupling capacitor can also be beneficial.
Digital Interface Inputs
Many of the same techniques that are recommended for the analog
interface inputs should also be used for the digital interface inputs.
It is important to minimize trace lengths, then make the input
trace impedances match the input termination (typically 50 W).
Each differential input pair (R
should be routed together using 50 W strip line routing techniques
and should be kept as short as possible. No other components,
e.g., no clamping diodes, should be placed on these inputs. Every
effort should be made to route these signals on a single layer
(component layer) with no vias.
Power Supply Bypassing
Bypassing each power supply pin with a 0.1 mF capacitor is
recommended. The exception is the case in which two or more
supply pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have one bypass capacitor.
The fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the side of the PC board opposite the AD9882, as that interposes
resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane Æ capacitor Æ power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PV
in PV
phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to pro-
vide separate regulated supplies for each of the analog circuitry
groups (V
D
can result in similarly abrupt changes in sampling clock
D
and PV
D
(the clock generator supply). Abrupt changes
D
).
X0+
, R
X0–
, R
XC+
, R
XC–
, and so on)
REV. A