LCMXO2280 Lattice Semiconductor, LCMXO2280 Datasheet - Page 24

• Manufacturer Part Number: LCMXO2280
• Description: (LCMXOxxx) MachXO Family
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applica-
tions.
Sleep Mode
The MachXO “C” devices (V
matically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin.
During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tri-
stated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power sup-
plies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11
compares the characteristics of Normal, Off and Sleep modes.
Table 2-11. Characteristics of Normal, Off and Sleep Modes
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch filter to prevent false triggering. An
external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal oper-
ation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid
low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC specifications por-
tion of this data sheet shows a detailed timing diagram.
Oscillator
Every MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the clock
tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated
programming bit to enable/disable the oscillator. The oscillator frequency ranges from 18MHz to 26MHz.
Configuration and Testing
The following section describes the configuration and testing features of the MachXO family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with one of the
VCCIO Banks (MachXO256: V
operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
SLEEPN Pin
Static Icc
I/O Leakage
Power Supplies VCC/VCCIO/VCCAUX
Logic Operation
I/O Operation
JTAG and Programming circuitry
EBR Contents and Registers
Characteristic
CC
= 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dra-
CCIO1
; MachXO640: V
Typical <10mA
Normal Range
User Defined
User Defined
Operational
Maintained
Normal
<10µA
High
CCIO2
2-21
; MachXO1200 and MachXO2280: V
Non Operational
Non-operational
Non-maintained
Tri-state
<1mA
Off
—
0
0
MachXO Family Data Sheet
Non operational
Non-operational
Non-maintained
Typical <100uA
Normal Range
www.DataSheet4U.com
Tri-state
<10µA
Architecture
Sleep
CCIO5
Low
) and can