W90220F Winbond Electronics Corp America, W90220F Datasheet
W90220F
Related parts for W90220F
W90220F Summary of contents
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... PA-RISC Embedded Controller 1 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 March 1999 W90220F Version 0.84 ...
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... Power Management Unit 4.8 Serial ICE interface 5. MEGACELLS 5.1 Functional Descriptions 5.1.1 Memory Controller 5.1.2 DMA Controller 5.1.3 PCI Bridge 5.1.4 Parallel Port Interface (PPI) 5.1.5 UART 2 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... Memory Controller 6.3.2 DMA Controller 6.3.3 PCI Bridge 6.3.4 Parallel Port Interface (PPI) 6.3.5 UART 6.3.6 Synchronous Serial Port Interface (SSI) 6.3.7 Timer Channels 7. PACKAGE DIMENSIONS 3 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... Internal Bus Interface Unit 32-bit CPU Internal Bus 32-bit Internal DMA bus PCI Memory DMA Bridge Controller Controller PCI Bus DRAM/Flash/ 8-bit-DMA/ ROM Port 16-bit-IO Bus W90220F Power Mang. Unit 3 Serial ICE RAM Serial ICE Bus Unit Parallel Port Sync. Serial Interface Port Version 0.84 ...
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... UART baud rate base on 14.318 Mhz A flexible hardware serial ICE port for monitor/update cpu status at any time 5 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... W90220F ...
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... The minimum duration of PERR# is one clock for each data phase that a data parity error is detected. An agent cannot report a PERR# until it has claimed the access by asserting DEVSEL# (for a target) and completed a data phase or is the master of the current transaction. W90220F Version 0.84 ...
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... IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on PDA[31:0]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. W90220F ability to ability to Version 0.84 ...
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... Bi-directional ECP Data bus, ED[0] is the most significant bit (msb). 11, 13 DRAM Row Address Strobe, Banks 0-1. These signals are used to select the DRAM row address. A High-to-Low transition on one of these signals causes a DRAM in the corresponding bank to latch the row address and begin an access. W90220F Version 0.84 ...
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... Memory controller Data bus bit 16-31 for both DRAM data 181,182,184- and ROM space data. Bit 16 is the most significant bit (msb). 191,193,195 1 COM1 serial data input from the communication link (modem or peripheral device). W90220F Version 0.84 ...
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... Vdd (for a mixed 5.0V/3.3V enviornment) 8,31,49,61,73 Global 3.3V Vdd ,89,112,133, 152,169,192 26,75,136,18 3.3V Vdd (for internal logic only) 3 198 3.3V Vdd (for internal PLL logic) 200 VSS (for internal PLL logic) 33,63,95,117, VSS (for internal logic) 146,165,196, 10,29,47,59, Global VSS 71,86,97,115, 131,149,167, 180,194 W90220F Version 0.84 ...
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... Cache-locking support in instruction cache Dynamic branch prediction 12 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... IMPLEMENTATION DEPENDENT FEATURES 4.6.1 MULTIMEDIA ENTENSION INSTRUCTION SET (Left for Blank) 4.6.2 MAC UNIT AND RELEATED INSTRUCTION SET (Left for Blank) 13 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... Blank) 4.6.5 LEVEL-0 DEBUG SFU (Left for Blank) 4.7 POWER MANAGEMENT UNIT (Left for Blank) 4.8 SP-ICE INTERFACE (Left for Blank) 14 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... IDE IO-channels connecting IDE devices provides 8-bit io-to-memory or memory-to-io transfer mode provides 8-, 16- and 32-bit memory-to-memory transfer modes 15 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... CS(s) to logic high. - DD[0:7] (in/out) : Birdirectional 8-bit data bus with bit 0 is the most significant bit. Operation Modes : (Left for Blank) 16 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... Provide DMA capability to accelerate moving data from parallel port interface to system memory ECP mode is also including : - High performance half-duplex forward and reverse channel 17 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... Peripherals drive this signal low to acknowledge "nInit". The host relies upon "PError" to deterine when it is permitted to drive the data signals. 18 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. 32-bit CPU bus 8 8 RX-FIFO (16x8) & Control Baud Rate Generator RX shift register OSC (14.318Mhz) SDI W90220F 8 RTS# Modem DTR# Control OUT1# Reg OUT2# CTS# Modem DSR# ...
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... The Irpt_TOR and the time-out counter will be cleared as the CPU reads one character from RX-FIFO. - The time-out counter is reset after a new character is received or after the CPU reads the RX-FIFO. 20 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. 32-bit CPU bus 16/32 FIFO Control RX-FIFO Logic (48x16/24x32) 16/32 SCLK/SYNC & Shift-in/out 32-bit RX-Shift reg control SYNC SCLK W90220F 16/32 16/32 SDI Version 0.84 ...
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... The transmit FIFO and receive FIFO is configued as 48x16 if "serial word length" <= 16, and will be configured as 24x32 if "serial word length" > 16. 22 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. = SCLK * (CFGL[0: Serial word length = CFGH[8:11 W90220F (5.1.6a) (5.1.6b) (5.1.6c) Version 0.84 ...
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... D2_3 D3_1 D3_2 D3_3 D1_1 D1_2 D1_3 D2_1 D2_2 D2_3 D3_1 D3_2 D3_3 D1_1 D1_2 D1_3 D2_1 D2_2 D2_3 D3_1 D3_2 D3_3 D1_1 D1_2 D1_3 D2_1 D2_2 D2_3 D3_1 D3_2 D3_3 W90220F D1_1 D1_2 D1_1 D1_2 D1_1 D1_2 D1_1 D1_2 Version 0.84 ...
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... OSC = 14.318Mhz) Typical OSC frequence is 14.318Mhz. Related Pins : (None) Operation Modes : (Left for Blank) 24 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... RAM bank 0 base register [8:15] R/W RAM bank 1 base register [0:7] R/W RAM bank 1 base register [8:15] R/W RAM bank 2 base register [0:7] R/W RAM bank 2 base register [8:15] R/W RAM bank 3 base register [0:7] R/W RAM bank 3 base register [8:15] R/W RAM Configuration register 0 [0:7] R/W RAM Configuration register 1 [0:7] R/W RAM Configuration register 2 [0:7] R/W RAM Configuration register 3 [0:7] W90220F (IO base (BA) : 0xf0000000) Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Read/Write ROM base address bit 8-15 Power-on Default : 0x0 ROMen1 W90220F Power-on Default : -- 6 7 Power-on Default : -- ROM bank_1 size Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. ROM size (*Basic unit) 64K 128K 256K 512K 16M Power-on Default : 0x0 ROMen3 W90220F 6 7 ROM bank_3 size Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Power-on Default : *note ROM2DW ROM1DW Data width Byte Halfword Word (reserved) Power-on Default : 0b'11011xx BK0only LA W90220F 6 7 ROM0DW 6 7 Reserved Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Wait States IOR echos BLAST#; IOW echos BRDY# TC0 echos RDY#; TC1 echos HLDA Read/Write Read/Write W90220F Power-on Default : -- 6 7 Power-on Default : -- Version 0.84 ...
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... A8 *(A20) A10 A20 A10 A29 A11 A29 A11 A28 A19 A28 A9 A27 A18 A27 A18 RAMTP0 16M COL ROW COL *(A18) A6 A18 A19 A8 A19 A20 A10 A20 A29 A11 A29 A28 A9 A28 A27 A27 A7 W90220F Version 0.84 ...
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... A13 A21 A12 A21 A12 Bank Selector Bank Selector A11 A9 A7 A8, A9 A6, A7 Power-on Default : 0x0 RAMen1 RAMen0 DIS384K W90220F A26 A17 A26 A25 A16 A25 A24 A15 A24 A23 A14 A23 A22 A13 A22 A21 A12 A21 Bank Selector ...
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... RAMconf2[2] ("CASPC") and RAMconf3[6:7] ("CASRD[0:1]") deter- mine CAS# precharge- and active-time during "DRAM read" cycles. 32 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. CAS# precharge-time (SYSCLK) 0.5 0 CAS# active-time (SYSCLK) 0.5 1 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. CAS# precharge-time (SYSCLK) 0.5 0 CAS# active-time (SYSCLK) 0.5 1.5 2.5 3 Power-on Default : 0x15 CASWR R2CRD[0:1] RAS# precharge-time (SYSCLK W90220F 6 7 R2CWR[0:1] Version 0.84 ...
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... RAM Configuration_3 Register (RAMconf3) Index : 0x2b Read/Write 34 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. RAS# to CAS# delay (SYSCLK RAS# to CAS# delay (SYSCLK Power-on Default : 0x09 W90220F Version 0.84 ...
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... Bits 6-7 CAS# active time during DRAM-read (CASRD[0:1]) 35 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond RA2CD[0:1] CA2RA Frequence of refresh cycle (us 240 960 Delay (SYSCLK W90220F 6 7 CASRD[0:1] Version 0.84 ...
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... Channel 1 Source Address Register R/W Channel 1 Target Address Register R/W Channel 1 Length Register R/W Channel 1 Mode Control Register R/W DMA IO Device 0 Bass Address R/W DMA IO Device 1 Base Address R Channel 0 Length Counter R Channel 1 Length Counter Read/Write Power-on Default : 0x00000000 Read/Write Power-on Default : 0x00000000 W90220F (IO base (BA) : 0xf0000000) Version 0.84 ...
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... Power-on Default : 0x00000000 Read/Write Power-on Default : 0x00000000 Target Address Register byte Target Address Register byte Target Address Register byte Target Address Register byte W90220F Version 0.84 ...
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... Read/write Power-on Default : 0x00000000 Read/write Power-on Default : 0x00000000 Reserved Reserved LEN1 LEN9-16 (LEN) Read/Write Power-on Default : 0x0000000f Read/Write Power-on Default : 0x00000000 ECPen TC M2M LEN0 DEM IOtype0 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond IOrec FIX DACK0L DACK1L Tout1-8 TO0 TO1 Reserved Tout0 (MOD0) CS0L (MOD1 (MOD0) Reserved (MOD1) W90220F Version 0.84 ...
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... IO device inserts wait state by asserting IORDY, the ready timeout counter starts to count. If the counter reach the Tout before read/write command is completed, the timeout flag TO0 or TO1 set. 40 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... DMA IO Device Bass Address (DBA0 and DBA1) Port address : 0xf0000220 Port address : 0xf0000224 41 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/write Power-on Default : 0xfffff000 Read/write Power-on Default : 0xfffff000 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond DBA0 DBA8- Reserved Read only Power-on Default : --- Read only Power-on Default : --- Reserved Reserved LENC1 Reserved LENC0 22 23 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond LENC9-16 Access Description R/W Master 0 Latency Register R/W Master 1 Latency Register R/W Master 2 Latency Register R/W Master 3 Latency Register Read/Write Power-on Default : 0x000003ff (IO base (BA) : 0xf0000000 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Reserved Reserved Reserved REQ0_reg[3:10] Read/Write Power-on Default : 0x000003ff Reserved REQ0_reg[0: W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond Reserved CPURST FIX REQ1_reg[3:10] Read/Write Power-on Default : 0x000003ff Reserved REQ1_reg[0: W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond Reserved REQ2_reg[3:10] Read/Write Power-on Default : 0x000003ff Reserved Reserved REQ2_reg[0: REQ3_reg[0:2] W90220F Version 0.84 ...
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... Description R/W Data Line Register R Device Status Register R/W Device Control Register R FIFO Status Register R/W FIFO Control Register R/W Interrupt Enable Register R Interrupt Identification Register R Data Register R/W Data FIFO R/W Command Register R/W Time Out Register - Reserve for PPI future extension W90220F 30 31 (IO base (BA) : 0xf0000000) Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Power-on Default : -- 8-bit Data Lines status Read only Power-on Default : --- SEL nFAULT EMPTY FULL CMDtrue W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/write Power-on Default : 0x0 DOE nAck_Ien nSELIN# nINIT nAUFD# nSTB# W90220F Version 0.84 ...
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... DRST 50 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read only Power-on Default : --- Read/Write Power-on Default : 0x0 PWord MOD W90220F RDTH Version 0.84 ...
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... Dfifo during reverse transfering. 51 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Device Operation Mode Test Mode Peripheral Emulation Mode Standard Mode PS2 Mode Fast Standard Mode ECP Mode W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read Threshold level PWord = 1 byte PWord = 4 bytes 16 bytes 12 bytes 8 bytes 1 byte Read/Write Power-on Default : 0x0 TC_Ien Temp_Ien Rda_Ien nFault_Ien 16 bytes 12 bytes 8 bytes 4 bytes 6 7 LOOP W90220F Version 0.84 ...
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... If IER[3] is set, and TC is asserted by DMA controller once DMA transfer is done IER[4] is set, and Dfifo is empty during "forward transfering" IER[5] is set, and data bytes received by Dfifo are exceeded the threshold level (defined in FCR[4:5] ) during "reverse transfering". W90220F 6 7 Irpt_nAck t Version 0.84 ...
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... If IER[6] is set, and a high-to-low transition is on "nFault" pin DCR[3] is set, and a low-to-high transition is on "nAck" pin. Read only Power-on Default : --- 8-bit Data of latched Lines status Read/write Power-on Default : --- Dfifo MSB byte W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond Dfifo LSB byte Read/write Power-on Default : --- Pended Command Code Read/write Power-on Default : --- TOUTcmp W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Access Description R Receiver Buffer Register W Transmitter Holding Register R/W Interrupt Enable Register R/W Divisor Latch Register (LS) R/W Divisor Latch Register (MS) R Interrupt Identification Register W90220F (IO base (BA) : 0xf0000000) Version 0.84 ...
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... Transmitter Holding Register R/W Interrupt Enable Register R/W Divisor Latch Register (LS) R/W Divisor Latch Register (MS) R Interrupt Identification Register W FIFO Control Register R/W Line Control Register R/W Modem Control Register R Line Status Register R MODEM Status Register R/W Time Out Register Read only Power-on Default : -- W90220F (IO base (BA) : 0xf0000000) Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond 8-bit Receiver Data Write only 8-bit Transmit Data Read/Write MOS_Ien RLS_Ien THRE_Ien RDA_Ien W90220F 6 7 Power-on Default : -- 6 7 Power-on Default : 0x0 6 7 Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/write Baud Rate Divisor (Low Byte) Read/write Baud Rate Divisor (High Byte) Read only Power-on Default : --- W90220F Power-on Default : 0x0 6 7 Power-on Default : 0x0 6 7 Version 0.84 ...
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... Third Transmitter Transmitter Holding Hoding Register Register Empty Empty (Irpt_THRE NOI Interrupt Reset control None -- Reading the LSR Receiver FIFO drops below the threshold level Reading the RBR Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Fourth MODEM Status CTS, DSR, DCD bits (Irpt_MOS) chang state or RI bit changes from high to low Write only Power-on Default : 0x1 Reserved DMOD TXRST Irpt_RDA trigger level (bytes Reading the MSR RXRST FMEN W90220F Version 0.84 ...
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... Two "stop bit" is generated when 6-, 7- and 8-bit word length is selected. 62 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Power-on Default : 0x0 EPAR PAR STOP W90220F 6 7 WLEN Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Character length 5 bits 6 bits 7 bits 8 bits Read/Write Power-on Default : 0x0 LOOP OUT2# OUT1# internally and SOUT pin is fixed logic 1. internally and OUT1# pin is fixed logic 1. W90220F 6 7 RTS# DTR# Version 0.84 ...
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... Bit 5 Parity Error indicator 64 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read only Power-on Default : --- W90220F Version 0.84 ...
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... Complement version of Clear to Send (CTS#) input Bits 4 DCD# state change 65 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read only Power-on Default : --- CTS# DDCD TERI W90220F 6 7 DDSR DCTS Version 0.84 ...
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... Time-Out comparator (TOUT_cmp), a Receiver Time-Out interrupt Irpt_ TOUT) is generated if TOR[0] = IER[ The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Power-on Default : 0x0 TOUT_cmp W90220F 6 7 Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Access Description R/W Data FIFO R/W High Configuration Register R/W Low Configuration Register R/W Control Register R/W Status Register Read/Write Power-on Default : -- Dfifo MSB Byte (IO base (BA) : 0xf0000000 W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond Dfifo LSB byte Read/Write Power-on Default : 0x0000 Reserved FACT MEXT SLEN[ WPF[0:3] W90220F Version 0.84 ...
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... Low Configuration Register (CFGL) Port address : 0xf0000386 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. FIFO will be configured as 48x16. Read/write Power-on Default : 0x0000 BPF[0:7] W90220F 6 7 Version 0.84 ...
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... When this bit is set, The RX-FIFO pointer will be cleared to 0, the RX-FIFO is empty immediately. 70 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond SCLKDIV[0:7] Read/Write Power-on Default : 0x0000 RXTH[0: Reserved TXTH[0:1] IntRxen 14 15 W90220F Version 0.84 ...
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... RXERR 8 9 IntTX INTRERR Bits 0 RX-FIFO data available 71 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Power-on Default : -- Reserved Reserved IntRX 14 15 W90220F Version 0.84 ...
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... No RX-FIFO overrun interrupt request RX-FIFO overrun interrupt request is pending Set = When RX-FIFO is overrun. Reset = Reset RX-FIFO or reset device. Bit 10-15 Reserved 72 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Access Description R/W Timer Control Register 1 R/W Timer Initial Control Register 1 R/W Timer Control Register 2 R/W Timer Initial Control Register 2 Read/Write Power-on Default : -- 24 Reserved W90220F (IO base (BA) : 0xf0000000) 31 Pre-scale Version 0.84 ...
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... Timer Initial Control Register1 (TICR2) Port address : 0xf0000043 74 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Read/Write Power-on Default : -- Timer Initial Count Read/Write Power-on Default : -- 24 Reserved Read/Write Power-on Default : -- W90220F 31 Pre-scale Version 0.84 ...
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... EI bits in the control register. When a timer reaches zero, the timer hardware reloads the counter with the value from the timer initial count register and continues decrementing. 75 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. Timer Initial Count W90220F Version 0.84 ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. CONDITION MIN 4.75 3.14 2.0 I OUT = 2,4,8 mA (*2) I OUT = -1,2,4 mA 2.4 (*2) F cpu = 100Mhz 2 0.4 V -10 (*1) -45 (* 0.4 V -10 (*3) ROMMEN#, DACK[0:1], CS[0:1], TC[0:1], DTR1#, RTS1#, W90220F MAX UNIT 5.25 V 3. 300 - Version 0.84 ...
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... RAS#[0:3], RCS#[0:3], ROM_OE#, ROM_RW#, IOR, IOW, nAutoFd, nStrob, SelectIn, nInit, SDO, MD[0:31], DD[0:7], PCICLK, SCLK, SYNC. CAS#[0:3], MA[0:11], WE#, PCIRST, GNT#[0:1], ED[0:7], C/BE[0:3], PDA[0:31], STOP#, PERR#, TRDY#, DEVSEL#, FRAME#, IRDY#, PPAR. CTS1#, DSR1#, RI1#, DCD1 rv1 t cv1 t wv Parameter W90220F t rv2 t cv2 Min Max Unit Version 0 ...
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... Chip select setup tome 78 The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond Parameter Parameter W90220F t dh Min Max Unit PCLK ...
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... The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from Winbond. 157 156 105 104 Detail F W90220F Dimension in inch Dimension in mm Symbol Min Nom Max Min Nom Max A 0.145 3.68 A 0.004 0.10 ...