W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 65

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
65
Bit 6
Bit 7
LSR[3:5] (BI, FE, PE) is revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR[3:6] (BI, FE, PE, OE) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER[5]=1. Read LSR clear Irpt_RLS.
Writing LSR is a null operation (not suggested).
Modem Status Register (MSR)
Port address : 0xf00003fe (COM1)
Bits 0
Bits 1
Bits 2
Bits 3
Bits 4
DCD#
0
Overrun Error indicator
RX FIFO Data Ready
Complement version of Data Carrier Detect (DCD#) input
Complement version of Ring Indicator (RI#) input
Complement version of Data Set Ready (DSR#) input
Complement version of Clear to Send (CTS#) input
DCD# state change
This bit is set to a logic 1 whenever the received character did not have a valid "parity bit".
An overrun error will occur only after the RX FIFO is full and the next character has been
completely received in the shift register. The ccharacter in the shift register is overwritten,
but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens
and is reset whenever the CPU reads the contents of the LSR.
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
0xf00002fe (COM2)
RI#
1
DSR#
2
CTS#
3
Read only
DDCD
4
Power-on Default : ---
TERI
5
DDSR
6
DCTS
7
W90220F
Version 0.84