AT91SAM7SE32 ATMEL Corporation, AT91SAM7SE32 Datasheet - Page 15

• Manufacturer Part Number: AT91SAM7SE32
• Description: (AT91SAM7SExxx) Flash microcontroller
• Manufacturer: ATMEL Corporation

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DataSheet
6. I/O Lines Considerations
6.1
6.2
6.3
6.4
6.5
6222AS–ATARM–23-Oct-06
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JTAG Port Pins
Test Pin
Reset Pin
ERASE Pin
SDCK Pin
AT91SAM7SE512/256/32 [Advance Information Summary]
TMS, TDI and TCK are schmitt trigger inputs and are not 5V-tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The
pin JTAGSEL integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations.
T h e T S T p i n i s u s e d f o r m a n u f a c t u r i n g t e s t o r f a s t p r o g r a m m i n g m o d e o f t h e
AT91SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. There is no constraint on the length of the reset pulse, and the reset controller
can guarantee a minimum pulse length. This allows connection of a simple push-button on the
NRST pin as system user reset, and the use of the NRST signal to reset all the components of
the system.
An external power-on reset can drive this pin during the start-up instead of using the internal
power-on reset circuit.
The NRST pin integrates a permanent pull-up of about 100 kΩ resistor to VDDIO.
This pin is not 5V-tolerant and has schmitt trigger input.
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to
high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high
during more than 220 ms to perform the re-initialization of the Flash.
The SDCK pin is dedicated to the SDRAM Clock and is an output-only without pull-up and is not
5V-tolerant. Maximum Output Frequency of this pad is 48 MHz at 3.0V and 25 MHz at 1.65V
with a maximum load of 30 pF.
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