UMA1021M/C2 Philips Semiconductors (Acquired by NXP), UMA1021M/C2 Datasheet - Page 11

• Manufacturer Part Number: UMA1021M/C2
• Description: UDA1380; Stereo Audio Coder-decoder For MD, CD And MP3
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
8
8.1
There are two clock systems:
The system frequency applied to pin SYSCLK is
selectable. The options are 256f
The system clock must be locked in frequency to the digital
interface signals.
Remark: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
system the IC is in, there is no auto sample rate conversion
detection circuitry.
The system can run in several modes, using the two clock
systems:
Table 1 WSPLL divider settings
2003 Apr 04
6.25 to 12.5
12.5 to 25
25 to 50
50 to 100
FREQUENCY (kHz)
A SYSCLK signal, coming from the system
A WSPLL which generates the internal clocks from the
incoming WSI signal.
Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
Stereo audio coder-decoder
for MD, CD and MP3
WORD SELECT
FUNCTIONAL DESCRIPTION
Clock modes
SEL_LOOP_DIV[1:0]
s
, 384f
00
01
10
11
s
, 512f
s
and 768f
s
.
PRE1
11
8
4
2
2
8.1.1
The WSPLL is meant to lock onto the WSI input signal, and
regenerates 256f
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
given in Table 1, using Fig.4 as a reference. This means
that the user must set the input range of the WSI input
signal.
In case the SYSCLK is used for clocking the complete
system (decimator including interpolator) the WSPLL must
be powered-down with bit ADC_CLK via the L3-bus
or I
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I
handbook, halfpage
2
C-bus.
WSPLL
WSI
s
REQUIREMENTS
Fig.4 WSPLL set-up.
(ADC and FSDAC)
and 128f
1536
1536
1536
DIV1
768
256f s
DIV1
(digital parts)
s
signals for the FSDAC and
128f s
2
C-bus register.
VCO FREQUENCY
Product specification
PRE1
VCO
MGU527
UDA1380
76 to 153
(MHz)