UMA1021M/C2 Philips Semiconductors (Acquired by NXP), UMA1021M/C2 Datasheet - Page 3

• Manufacturer Part Number: UMA1021M/C2
• Description: UDA1380; Stereo Audio Coder-decoder For MD, CD And MP3
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
1
1.1
2003 Apr 04
2.4 to 3.6 V power supply
5 V tolerant digital inputs (at 2.7 to 3.6 V power supply)
24-bit data path for Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
Selectable control via L3-bus microcontroller interface
or I
L3-bus and I
Remark: This device does not have a static mode.
Supports sample frequencies from 8 to 55 kHz for the
ADC part, and 8 to 100 kHz for the DAC part. The ADC
does not support DVD audio (96 kHz audio), only
Mini-Disc (MD), Compact-Disc (CD) and Moving Picture
Experts Group Layer-3 Audio (MP3). For playback
8 to 100 kHz is specified. DVD playback is supported
Power management unit:
– Separate power control for ADC, Automatic Volume
– Analog blocks like ADC and Programmable Gain
– When ADC and/or DAC are powered-down, the
Remark: By default, when the IC is powered-up, the
complete chip will be in the Power-down mode.
ADC part and DAC part can run at different frequencies,
either system clock or Word Select PLL (WSPLL)
ADC and PGA plus integrated high-pass filter to cancel
DC offset
The decimation filter is equipped with a digital Automatic
Gain Control (AGC)
Mono microphone input with Low Noise Amplifier (LNA)
of 29 dB fixed gain and Variable Gain Amplifier (VGA)
from 0 to 30 dB in steps of 2 dB
Integrated digital filter plus DAC
Separate single-ended line output and one stereo
headphone output, capable of driving a 16
headphone driver has a built-in short-circuit protection
with status bits which can be read out from the
L3-bus or I
Digital silence detection in the interpolator (playback)
with read-out status via L3-bus or I
Easy application.
Stereo audio coder-decoder
for MD, CD and MP3
FEATURES
Control (AVC), DAC, Phase Locked Loop (PLL) and
headphone driver
Amplifier (PGA) have a block to power-down the bias
circuits
clocks to these blocks are also stopped to save
power.
2
C-bus interface; choice of 2 device addresses in
General
2
C-bus interface
2
C-bus mode
2
C-bus interface
load. The
3
1.2
1.3
1.4
Slave BCK and WS signals
I
MSB-justified format compatible
LSB-justified format compatible.
Select option for digital output interface: either the
decimator output (ADC signal) or the output signal of the
digital mixer which is in the interpolator DSP
Selectable master or slave BCK and WS signals for
digital ADC output
Remark: SYSCLK must be applied in WSPLL mode and
master mode
I
MSB-justified format compatible
LSB-justified format compatible.
ADC plus decimator can run at either WSPLL,
regenerating the clock from WSI signal, or on SYSCLK
Stereo line input with PGA: gain range from 0 to 24 dB
in steps of 3 dB
LNA with 29 dB fixed gain for mono microphone input,
including VGA with gain from 0 to 30 dB in steps of 2 dB
Digital left and right independent volume control and
mute from +24 to 63.5 dB in steps of 0.5 dB.
2
2
S-bus format
S-bus format
Multiple format data input interface
Multiple format data output interface
ADC front-end features
Product specification
UDA1380