UMA1021M/C2 Philips Semiconductors (Acquired by NXP), UMA1021M/C2 Datasheet - Page 14

• Manufacturer Part Number: UMA1021M/C2
• Description: UDA1380; Stereo Audio Coder-decoder For MD, CD And MP3
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
In applications in which a 2 V (RMS) input signal is used,
a 12 k resistor must be used in series with the input of the
ADC (see Fig.7). This forms a voltage divider together with
the internal ADC resistor and ensures that the voltage,
applied to the input of the IC, never exceeds 1 V (RMS).
Using this application for a 2 V (RMS) input signal, the
switch must be set to 0 dB. When a 1 V (RMS) input signal
is applied to the ADC in the same application, the gain
switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 2; the power supply
voltage is assumed to be 3 V.
Table 2 Application modes using input gain stage
8.3
The decimation from 128f
first stage realizes a
factor of 16. The second stage consists of 3 half-band
filters, each decimating by a factor 2. The filter
characteristics are shown in Table 3.
2003 Apr 04
handbook, halfpage
Present
Absent
Stereo audio coder-decoder
for MD, CD and MP3
Pin numbers for UDA1380HN in parentheses.
RESISTOR
input signal
2 V (RMS)
(12 k )
Decimation filter (ADC)
Fig.7 ADC front-end with PGA (line input).
external
resistor
12 k
---------- -
sin
x
INPUT GAIN
VINL,
VINR
x
SWITCH
s
characteristic with a decimation
0 dB
6 dB
0 dB
6 dB
is performed in two stages. The
(27,
31,
1
29)
12 k
V REF
V DDA = 3 V
0.5 V (RMS)
PGA
MAXIMUM
2 V (RMS)
1 V (RMS)
1 V (RMS)
VOLTAGE
INPUT
MGU529
14
Table 3 Decimation filter characteristics
8.3.1
The UDA1380 is equipped with an overload detector which
can be read out from the L3-bus or I
In practice the output is used to indicate whenever the
output data, in either the output of the left or right channel,
exceeds 1 dB (the actual figure is 1.16 dB) of the
maximum possible digital swing. When this condition is
detected output bit OVERFLOW in the L3-bus register is
forced to logic 1 for at least 512f
f
8.3.2
The decimator is equipped with a digital volume control.
This volume control is separate for left and right, and can
be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via
the L3-bus or I
to 63.5 dB and mutes in steps of 0.5 dB.
8.3.3
The decimator is equipped with a dB-linear mute which
mutes the signal in 256 steps of 0.5 dB.
8.3.4
The decimation filter is equipped with an AGC block. This
function is intended, when enabled, to keep the output
signal at a constant level. The AGC can be used for
microphone applications in which the distance to the
microphone is not always the same.
The AGC can be enabled via an L3-bus or I
setting the bit to logic 1. In that case it bypasses the digital
volume control.
Via the L3-bus or I
settings of the AGC, like the attack and decay settings and
the target level settings, can be made.
Remark: The DC filter before the decimation filter must be
enabled by setting the L3-bus or I
to logic 0 when AGC is in operation; otherwise the output
will be disturbed by the DC offset added in the ADC.
s
Pass-band ripple
Stop band
Dynamic range
Digital output
level
= 44.1 kHz). This time-out is reset for each infringement.
ITEM
O
V
M
AGC
OLUME CONTROL
VERLOAD DETECTION
UTE
2
FUNCTION
C-bus interface. The range is from +24 dB
2
C-bus interface also some other
at 0 dB input
CONDITION
0 to 0.45f
0 to 0.45f
>0.55f
analog
s
s
s
s
2
cycles (11.6 ms at
C-bus bit SKIP_DCFIL
2
Product specification
C-bus interface.
UDA1380
VALUE (dB)
2
C-bus bit by
>135
0.01
1.5
70