UMA1021M/C2 Philips Semiconductors (Acquired by NXP), UMA1021M/C2 Datasheet - Page 22

• Manufacturer Part Number: UMA1021M/C2
• Description: UDA1380; Stereo Audio Coder-decoder For MD, CD And MP3
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9.1
The exchange of data and control information between the
microcontroller and the UDA1380, is accomplished
through a serial hardware interface comprising the
following pins:
Information transfer via the microcontroller bus is
organized LSB first, and in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: address mode and data transfer mode.
Inside the microcontroller interface there is a hand-shake
mechanism which takes care of proper data transfer from
the microcontroller interface clock to the destination clock
domains. This means that when data is sent to the
microcontroller interface, the system clock must be
running.
9.2
The device addressing mode is used to select a device for
subsequent data transfer. The address mode is
characterized by the signal on pin L3MODE being LOW
and a burst of 8 pulses on pin L3CLOCK/SCL,
accompanied by an 8 bit device address on
pin L3DATA/SDA. The fundamental timing is shown in
Figs 14 and 15.
Table 6 Selection of data transfer
Table 6 shows that there are two types of data transfers:
DATA and STATUS which can be read and written.
Table 6 also shows that the DATA and STATUS read and
write actions are combined.
2003 Apr 04
BIT 1
DOM
L3DATA/SDA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK/SCL: microcontroller interface clock line.
Stereo audio coder-decoder
for MD, CD and MP3
0
0
1
1
Introduction
Device addressing
BIT 0
DOM
0
1
0
1
not used
not used
DATA and STATUS write or pre-read
DATA and STATUS read
TRANSFER
22
The device address consists of one byte, which is split-up
in two parts:
9.3
The UDA1380 acts as a slave receiver or a slave
transmitter. Therefore the signals L3CLOCK and L3MODE
are only input signals. The data signal L3DATA is a
bidirectional line. The UDA1380 slave address is shown in
Table 7.
Table 7 L3 slave address
9.4
After sending the device address, including the flags (the
DOM bits) whether information is read or written, one byte
is sent with the destination register address using 7 bits,
and one bit which signals whether information will be read
or written. The fundamental timing for L3 is given in Fig.19.
Basically there are three forms for register addressing:
Remarks:
(MSB)
Bits 7 to 2 represent a 6-bit device address. In the
UDA1380 this is 000001
Bits 1 to 0 called Data Operation Mode, or DOM bits,
represent the type of data transfer according to Table 6.
Register addressing for L3 write: the first bit is a logic 0
indicating a write action to the destination register,
followed by seven register address bits
Prepare read addressing: the first bit of the byte is
logic 1; signalling data will be read from the register
indicated
The read action itself: in this case the device returns a
register address prior to sending data from that register.
When the first bit of the byte is logic 0, the register
address was valid, in case the first bit is a logic 1 the
register address was invalid.
Each time a new destination address needs to be
written, the device address must be sent again
When addressing the device for the first time after
power-up of the device, at least one L3 clock-cycle must
be given to enable the L3 interface.
0
Slave address
Register addressing
0
0
BIT
0
Product specification
UDA1380
0
(LSB)
1