ISL5239 Intersil Corporation, ISL5239 Datasheet
ISL5239
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ISL5239 Summary of contents
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... The ISL5239 supports log of power, linear magnitude, and linear power based pre-distortion, utilizing two Look-Up Table (LUT) based algorithms for the pre-distortion correction. The ...
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... Functional Block Diagram ISL5239 Pre-Distortion Linearizer IIN<17:0> OFFSET BYPASS BYPASS BINARY QIN<17:0> HALF BAND CLKOUT FILTER / DE-MUX / ISTRB INPUT TYPE (PAR/SERIAL) TMS TDI TCK JTAG TRST TDO TRIGIN PD MAG. THRESHOLD MAX COMPARE MIN uP TRIG SEL TRIG IFIP I,Q INPUT DELAY PD I,Q COUNT PD MAG ...
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... A<5:0>, CS, RD, and WR to write to and read from the devices internal control registers. When the host system asserts CS and RD simultaneously, P<15:0> output bus, under all other conditions input bus. Bit 15 is the MSB. 3 ISL5239 196 CABGA TOP VIEW 4 ...
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... DC tree output. NAND tree output for DC threshold test. Do not connect for normal operation. JTAG TEST ACCESS PORT TMS I JTAG Test Mode Select. Internally pulled up. TDI I JTAG Test Data In. Internally pulled up. TCK I JTAG Test Clock. TRST I JTAG Test Reset (Active Low). Internally pulled-up. TDO O JTAG Test Data Out. 4 ISL5239 DESCRIPTION ...
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... ADC’s are also supported. The block diagram on page 1 shows the internal functional units within the ISL5239. In the following sections each functional unit is described. The operation of the ISL5239 is controlled by the register map listed in Table 3. Detailed descriptions for each control/status register are given in Tables 4 through 48 ...
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... RF amplifier’s behavior and compensate. The average power into the amplifier is computed and transmitted serially off chip. The external 6 ISL5239 circuits compute one or two memory effect coefficients which are combined with the complex delta values in the LUT to derive the final distortion vector. The distortion ...
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... NORMALIZED FREQUENCY (NYQUIST=1) FIGURE 7. x2, IFC FREQUENCY RESP. 7 ISL5239 I FIGURE 7A. x2, IFC FREQUENCY RESP. WITH FOLDING. Complex: The complex operating mode simply shifts the complex baseband signal up by Fs/4 without any filtering or real conversion. The operation of the IF converter in this mode is shown in Figure 8. ...
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... Figure 10. FIGURE 11. IMBALANCE CORRECTION The Output formatter also provides DC offset correction to 1/4 LSB for 18-bit outputs to reduce analog DC offsets 8 ISL5239 introduced in external D/A conversion and modulation circuits which can degrade system performance by causing carrier feed through in complex baseband systems, or spurs at DC for IF systems. ...
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... The advanced trigger mode is used in capture mode only. With the feedback capture operations being analogous to the input memory, one feedback memory 9 ISL5239 exception is its control register 0x08, bits 14:0. It has 10 LSBs of available capture space. Advanced Trigger Capture Mode Sequence: The control register 0x0e, bit 13:12 input capture status, should be in IDLE ...
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... The first of these transitions causes a trigger to be detected and the remaining triggers during the capture sequence is ignored. 10 ISL5239 To invoke the user invoked trigger, 0x04, 5:4, set to processor, the programmer writes a TRIGGER to the 0x04, bit 6 processor trigger register. After a TRIGGER is in the field, the user initiates the trigger by just writing to that register ...
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... Microprocessor Interface The microprocessor interface allows the ISL5239 to appear as a memory mapped peripheral to the µP. All registers can be accessed through this interface. The interface consists bit bidirectional data bus, P<15:0>, six bit address bus, A<5:0>, a write strobe (WR), a read strobe (RD) and a chip enable (CE) ...
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... WR. 0x28 selects the auto increment mode. 2. Perform a direct write to control word 0x29 by setting up the address on A<5:0>, data on P<15:0>, and generating 12 ISL5239 a rising edge on WR. 0x29 selects the coefficient address for Perform a direct write to control word 0x2a by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR ...
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... I/O supplies to their respective regulation levels in a maximum time frame of a 100 ms, moderates the stresses placed on both, the power supply and the ISL5239. When powering down, simultaneous removal is preferred, but It is also safe to remove the I/O supply prior to the core supply. If the core power is removed first, the I/O supply should also be removed within 10-100mS ...
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... C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major A process or design changes. 14 ISL5239 Thermal Information Thermal Resistance (Typical, Notes 1, 2) 196 BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Hold Time FB<19:0> from FBCLK Delay Time from CLK to SERSYNC Delay Time from CLK to SEROUT Delay Time from CLK to SERCLK in Period_32 Mode Delay Time from CLK to SERCLK in Period_64 or Period_128 Modes Setup Time from SERIN to CLK (Note 7) 15 ISL5239 V = 1.8± 5 3.3 ± 5 -40 CCC CCIO ...
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... Can be asynchronous to CLK, specification guarantying which CLK edge the device begins the read cycle on. AC Test Load Circuit SWITCH S † TEST HEAD CAPACITANCE Waveforms t CLK CLK CLK RPW RESET FIGURE 15. CLOCK AND RESET TIMING 16 ISL5239 V = 1.8± 5 3.3 ± 5 -40 CCC CCIO A SYMBOL t DHS t PDC t DS1 t DH1 ...
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... WSC t WPWL WR t WPWH t BDW 4 CLK CYCLES BUSY t CSW VALID A<5:0> t PSW t VALID P<15:0> FIGURE 21. MICROPROCESSOR WRITE TIMING Programming Information 17 ISL5239 t DH VALID TRIGIN TRIGOUT VALID TMS, TDI BUSY t CHW ASW AHW A<5:0> PHW P<15:0> CLK t PDC t DH1 t DS1 FIGURE 18. TRIGGER PORT TIMING TCK ...
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... R/W IF Converter R/W Correction Filter 29 R ISL5239 TABLE 2. CONTROL REGISTER MAP FUNCTION Global Chip Control Chip ID Control Status Control Length of Input Memory Loops Input Memory Capture Mode and Trigger Delay Operating Modes Feedback Memory Capture Mode and Trigger Delay Magnitude Threshold Minimum Value ...
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... ID_Index description, reading ChipID with ID_Index = PAIR_0 returns the ASCII code for “AB”. The ASCII code for “A” is 0x41, and the ASCII code for “B” is 0x42; therefore, ChipID would have the value 0x4142. 19 ISL5239 TABLE 2. CONTROL REGISTER MAP (Continued) Control I-to-I (hm) Coefficient ...
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... When high, indicated the input formatter and interpolator block performed an illegal operation since the last clear status command. 0 Serial Mode Error Active When high, indicates the input formatter and interpolator block is performing an illegal operation. Not impacted by the clear status command. 20 ISL5239 TABLE 5. CONTROL DESCRIPTION TABLE 6. STATUS DESCRIPTION ...
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... When control word 0x06, bit 15 is set to 0, delay mode, values selectable from 2 When control word 0x06, bit 15 is set to 1, advance mode, value selectable from 2 21 ISL5239 TABLE 7. CONTROL TYPE: CAPTURE MEMORY, ADDRESS: 0x04 DESCRIPTION TABLE 8. LENGTH OF INPUT MEMORY LOOP ...
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... BIT FUNCTION 15:11 Reserved Not used. 10:0 Memory Address Index into memory value. Default = 0. Selectable from 2 22 ISL5239 TABLE 10. OPERATING MODES TYPE: CAPTURE MEMORY, ADDRESS: 0x07 DESCRIPTION TYPE: CAPTURE MEMORY, ADDRESS: 0x08 DESCRIPTION TYPE: CAPTURE MEMORY, ADDRESS: 0x09 DESCRIPTION ...
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... Pre-distorter is active and processing Pre-distorter is bypassed. 0 Reset Software generated logic reset, which when high, resets the pre-distorter circuitry. Low is default. 23 ISL5239 TABLE 15. MEMORY DATA LSW TYPE: CAPTURE MEMORY, ADDRESS: 0x0c DESCRIPTION TABLE 16. MEMORY DATA MSW TYPE: CAPTURE MEMORY, ADDRESS: 0x0d DESCRIPTION TABLE 17 ...
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... BIT FUNCTION 15:0 LUT Data Q Imaginary distortion data written to or read back from LUT. Selectable as (-0.5...(0.5-increment)) in increments ISL5239 TABLE 20. MAGNITUDE FUNCTION CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x11 DESCRIPTION -1 . Note: Setting the LSB of this value permits rounding of the resulting TYPE: PRE-DISTORTER, ADDRESS: 0x12 ...
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... Power Integrator <15:0> Power integrator LSW. TABLE 31. MEMORY EFFECT POWER INTEGRATOR MSW BIT FUNCTION 15:0 Power Integrator <31:16> Power integrator MSW. 25 ISL5239 TABLE 26. LOOK-UP TABLE REAL DATA TYPE: PRE-DISTORTER, ADDRESS 0x17 DESCRIPTION . Default = 0. TABLE 27. MEMORY EFFECT CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x18 DESCRIPTION 2 , low to select B (default). ...
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... Set high to clear all status bits, low for normal status bit updates. 1 Bypass Set high (default) to bypass the correction filter, low to enable processing. 0 Reserved Not used. 26 ISL5239 TABLE 32. STATUS TYPE: PRE-DISTORTER, ADDRESS: 0x1d DESCRIPTION TABLE 33. CONTROL TYPE: IF CONVERTER, ADDRESS: 0x20 DESCRIPTION TABLE 34. STATUS ...
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... Set high to clear all status bits, low to enable bits to be active. 1 Bypass Set high (default) to bypass, low to enable output processing. 0 Reserved Not used. 27 ISL5239 TABLE 36. COEFFICIENT INDEX TYPE: CORRECTION FILTER, ADDRESS: 0x29 DESCRIPTION TABLE 37. COEFFICIENT VALUE TYPE: CORRECTION FILTER, ADDRESS: 0x2a DESCRIPTION TABLE 38. STATUS ...
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... Q DC offset master register containing the upper four bits of the Q DC offset. TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x38 BIT FUNCTION 15 Offset <15:0> offset master register containing the lower 16 bits of the Q DC offset. 28 ISL5239 TABLE 40. I-to-I (HM) COEFFICIENT DESCRIPTION (1-15) . TABLE 41. Q-to-I (KM) COEFFICIENT DESCRIPTION TABLE 42. I-to-Q (LM) COEFFICIENT DESCRIPTION TABLE 43 ...
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... When high indicates that the output data conditioner saturated at least one sample since the last control word 0x30, bit 2 command Channel Status When high indicates that the output data conditioner saturated at least one sample since the last control word 0x30, bit 2 command. 29 ISL5239 TABLE 48. STATUS DESCRIPTION ...
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... Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 30 ISL5239 A V196.15x15 196 BALL PLASTIC BALL GRID ARRAY PACKAGE ...