ISL5239 Intersil Corporation, ISL5239 Datasheet - Page 11

• Manufacturer Part Number: ISL5239
• Description: Pre-distortion Linearizer
• Manufacturer: Intersil Corporation

Microprocessor Interface
The microprocessor interface allows the ISL5239 to appear
as a memory mapped peripheral to the µP. All registers can
be accessed through this interface. The interface consists of
a 16 bit bidirectional data bus, P<15:0>, six bit address bus,
A<5:0>, a write strobe (WR), a read strobe (RD) and a chip
enable (CE). The interface is configured for separate read
and write strobe inputs.
The processor interface provides a simple parallel
Data/Control/Address bus for monitoring and controlling its
operation. The processor interface is asynchronous to the
CLK, and BUSY signal is included to indicate when read and
write operations are complete.
The register configuration is master/slave, where the slave
registers are updated from the masters and all reads access
the slaves.
The master registers are clocked by the µP WR strobe, are
writable and cleared by a hard reset. The slave registers are
clocked by CLK, and are readable and cleared by either a
hard or soft reset. The transfer of configuration data from the
master register to the slave register occurs synchronously
after an event and requires a four clock synchronization
period.
The µP can perform back-to-back accesses to the register,
but must maintain four f
the same address. This limits the maximum µP access rate
for the RAM to 125MHz/4 = 31.25MHz.
The address map and bit field details for the microprocessor
interface is shown in the Tables 2-48. The procedures for
reading and writing to this interface are provided below.
Microprocessor Read/Write Procedure
The ISL5239 offers the user microprocessor read/write
access to all of the configuration registers and the capture
memory.
Configuration Read/Write Procedure
Write Access to the Configuration Master
Registers
Perform a direct write to the configuration master registers
by setting up the address A<5:0>, data P<15:0>, enabling the
CS input, and generating WR strobe. The rising edge of the
WR initiates the transfer to the master register. Registers may
be written in any order.
1. Write the global control register 0x00.
2. Write all remaining registers sequentially.
3. Load all IFIP, PD, IFC, CM and ODC coefficients and
control words.
CLK
periods between accesses to
11
ISL5239
Read Access to the Configuration Slave Registers
LUT Read/Write Procedure
Write Access to the LUT Memory
Read Access to the LUT
1. Perform a direct read of a configuration register by
1. Perform a direct write to control word 0x13 by setting up
2. Perform a direct write to any/all control words 0x14, 0x15,
3. Perform a direct write to control word 0x17 by setting up
1. Perform a direct write to control word 0x13 by setting up
2. Perform a direct read of any/all control words 0x14, 0x15,
3. Perform a direct read of control word 0x17 by dropping the
dropping the RD line low to transfer data from the register
selected by A<5:0> onto the data bus P<15:0>.
the address on A<5:0>, data on P<15:0>, and generating
a rising edge on WR. 0x13 selects the auto increment
mode and the LUT address as specified in bit 9:0.
or 0x16, in any order, by setting up the address on
A<5:0>, data on P<15:0>, and generating a rising edge on
WR.
the address on A<5:0>, data on P<15:0>, and generating
a rising edge on WR. The WR updates the contents of
0x014-0x017 and performs the auto increment, if
enabled.
the address on A<5:0>, data on P<15:0>, and generating
a rising edge on WR. 0x13 selects the auto increment
mode and the LUT address as specified in bit 9:0.
0x16, in any order, by dropping the RD line low to transfer
data from the slave register selected by A<5:0> onto the
data bus P<15:0>.
RD line low to transfer data from the slave register
selected by A<5:0> onto the data bus P<15:0>. Reading
P<15:0>
P<15:0>
A<5:0>
A<5:0>
FIGURE 13. CONFIGURATION WRITE TRANSFER
FIGURE 14. CONFIGURATION READ TRANSFER
RD
WR
RD
WR
HI-Z
DATA VALID
0X00
0x00
xxxx
0X01 0X02
0x01 0x02
0X03
0x03
0X04
0x04
0X05
0x05