ISL5585 Intersil Corporation, ISL5585 Datasheet - Page 17

• Manufacturer Part Number: ISL5585
• Description: 3.3 Volt Ringing Slic Family For Voice Over Broadband (VOB)
• Manufacturer: Intersil Corporation

Ringing Input
The ringing input, V
impedance allows the use of low value capacitors for AC
coupling the ring signal. The V
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95V
maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4V
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R
capacitor C
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P
The terms t
interval is t
ratio t
P
RT
RNG
and C
R
=
:t
P
S
r
, and the silent interval power, P
r
is 1:2.
RT
R
RT
×
R
and the silent interval is t
------------- -
t
. The resistor R
r
and t
sets the trip response time. Most applications will
+
t
r
t
s
+
S
P-P
RS
P
represent the cadence. The ringing
s
, is a high impedance input. The high
×
. The low signal levels are compatible
------------- -
t
r
t
+
s
t
RT
s
17
RS
sets the trip threshold and the
input is enabled only
S
. The typical cadence
P-P
s
. Hence, the
.
(EQ. 57)
ISL5585
The quiescent power of the device in the ringing mode is
defined in Equation 58.
The total power during the ringing interval is the sum of the
quiescent power and loading power:
For sinusoidal waveforms, the average current, I
defined in Equation 60.
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Unbalanced Ringing
The ISL5585GCM offers Unbalanced Ringing mode (010).
This feature accommodates some Analog PBX Trunk Lines
that require the Tip terminal to be held near ground for the
duration of the ringing bursts. The Tip terminal is offset to
0V’s with an internal current source that is applied to the
inverting input of the Tip amplifier. This reduces the
differential ringing gain to 40V/V. The Ring terminal will
center at Vbh/2 and swing from -Vbh to ground. As in
Balanced Ringing, off hook detection is accomplished by
sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.
Forward Loop Back
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
FIGURE 13. FORWARD LOOP BACK INTERNAL TERMINATION
P
P
I
AVG
r Q
r
( )
=
=
P
=
r Q
 
 
( )
2
-- -
π
V
BH
----------------------------------------- -
Z
+
REN
V
V
×
BH
RMS
RING
I
BHQ
TIP
+
×
R
I
×
AVG
LOOP
+
V
2
BL
–
----------------------------------------- -
Z
×
REN
I
BLQ
600Ω
V
2
RMS
+
+
R
V
LOOP
CC
TIP AMP
RING AMP
×
I
CCQ
AVG
(EQ. 58)
(EQ. 59)
(EQ. 60)
, is