PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 111

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

TABLE 15-2: PIC17CXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
TABLWT
TLRD
TLWT
TSTFSZ
XORWF
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Legend: Refer to Table 15-1 for opcode field descriptions.
Note 1: 2’s Complement method.
1996 Microchip Technology Inc.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
9: These instructions are not available on the PIC17C42.
register (WREG) is required to be affected, then f = WREG must be specified.
the LSB of the PC (PCL)
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
NOP is executed.
t,i,f
t,f
t,f
f
f,d
f,b
f,b
f,b
f,b
f,b
k
k
k
—
k
k
k
k
k
k
k
—
k
—
—
k
k
Description
Table Write
Table Latch Read
Table Latch Write
Test f, skip if 0
Exclusive OR WREG with f
Bit Clear f
Bit Set f
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
ADD literal to WREG
AND literal with WREG
Subroutine Call
Clear Watchdog Timer
Unconditional Branch
Inclusive OR literal with WREG
Long Call
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP Mode
Subtract WREG from literal
Exclusive OR literal with WREG
Cycles
1 (2)
1 (2)
1 (2)
2
1
1
1
1
1
1
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
1010 11ti ffff ffff
1010 00tx ffff ffff
1010 01tx ffff ffff
0011 0011 ffff ffff
0000 110d ffff ffff
1000 1bbb ffff ffff
1000 0bbb ffff ffff
1001 1bbb ffff ffff
1001 0bbb ffff ffff
0011 1bbb ffff ffff
1011 0001 kkkk kkkk
1011 0101 kkkk kkkk
111k kkkk kkkk kkkk
0000 0000 0000 0100
110k kkkk kkkk kkkk
1011 0011 kkkk kkkk
1011 0111 kkkk kkkk
1011 1000 uuuu kkkk
1011 101x kkkk uuuu
1011 0000 kkkk kkkk
1011 1100 kkkk kkkk
0000 0000 0000 0101
1011 0110 kkkk kkkk
0000 0000 0000 0010
0000 0000 0000 0011
1011 0010 kkkk kkkk
1011 0100 kkkk kkkk
MSb
16-bit Opcode
LSb
PIC17C4X
Status
Affected
OV,C,DC,Z
OV,C,DC,Z
DS30412C-page 111
GLINTD
TO, PD
TO,PD
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
Z
Notes
5
6,8
6,8
6,8
7
7
4,7
9
9
7
7
7