PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 74

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

PIC17C4X
12.1.2
To select 16-bit mode, the T16 bit must be set. In this
mode TMR1 and TMR2 are concatenated to form a
16-bit timer (TMR2:TMR1). The 16-bit timer incre-
ments until it matches the 16-bit period register
(PR2:PR1). On the following timer clock, the timer
value is reset to 0h, and the TMR1IF bit is set.
When selecting the clock source for the16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care.” When TMR1CS is clear, the
timer increments once every instruction cycle (Fosc/4).
When TMR1CS is set, the timer increments on every
falling edge of the RB4/TCLK12 pin. For the 16-bit timer
to increment, both TMR1ON and TMR2ON bits must be
set (Table 12-1).
FIGURE 12-4: TMR1 AND TMR2 IN 16-BIT TIMER/COUNTER MODE
TABLE 12-2:
Address
DS30412C-page 74
16h, Bank 3
17h, Bank 3
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
12h, Bank 3
13h, Bank 3
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
RB4/TCLK12
TIMER1 & TIMER2 IN 16-BIT MODE
shaded cells are not used by Timer1 or Timer2.
Fosc/4
Name
TCON1
TCON2
TMR1
TMR2
PIR
PIE
PR1
PR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
SUMMARY OF TIMER1 AND TIMER2 REGISTERS
TMR1CS
(TCON1<0>)
0
1
Timer1 register
Timer2 register
Timer1 period register
Timer2 period register
CA2ED1 CA2ED0
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
RBIF
RBIE
Bit 7
PEIF
DC1
DC1
DC9
DC9
—
TMR1ON
(TCON2<0>)
TMR3IF
TMR3IE
T0CKIF
Bit 6
DC0
DC0
DC8
DC8
—
TM2PW2
CA1ED1
TMR2IF
TMR2IE
STKAV
Bit 5
T0IF
DC7
DC7
—
CA1ED0
TMR1IF
TMR1IE
GLINTD
TMR2 x 8
Bit 4
INTF
PR2 x 8
DC6
DC6
—
—
Comparator x16
Comparator<8>
CA2IF
CA2IE
Bit 3
PEIE
DC5
DC5
12.1.2.1
When TMR1CS is set, the 16-bit TMR2:TMR1 incre-
ments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchro-
nized by the internal phase clocks twice every instruc-
tion cycle. This causes a delay from the time a falling
edge
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
TABLE 12-1:
T16
TO
—
—
TMR2ON
1
0
x
TMR3CS TMR2CS TMR1CS 0000 0000
T0CKIE
appears
CA1IF
CA1IE
Bit 2
DC4
DC4
PD
TMR1 x 8
—
—
PR1 x 8
EXTERNAL CLOCK INPUT FOR
TMR1:TMR2
TMR1ON
TXIF
TXIE
Bit 1
T0IE
DC3
DC3
TURNING ON 16-BIT TIMER
—
—
—
on
1
1
0
RB4/TCLK12
RCIE
Equal
RCIF
INTE
Reset
Bit 0
DC2
DC2
1996 Microchip Technology Inc.
—
—
—
16-bit timer
(TMR2:TMR1) ON
Only TMR1 increments
16-bit timer OFF
xxxx xxxx
xxxx xxxx
0000 0010
0000 0000
0000 0000
--11 11--
xxxx xxxx
xxxx xxxx
xx-- ----
xx0- ----
xxxx xxxx
xxxx xxxx
Power-on
Value on
Set Interrupt TMR1IF
(PIR<4>)
Reset
Result
to
other resets
Value on all
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0010
0000 0000
0000 0000
--11 qq--
uuuu uuuu
uuuu uuuu
uu-- ----
uu0- ----
uuuu uuuu
uuuu uuuu
the
(Note1)
time