PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 125

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
1996 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register 'f'
Inclusive OR WREG with f
[ label ]
0
d
(WREG) .OR. (f)
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in regis-
ter 'f'.
1
1
IORWF
Z
Read
0000
Q2
0x13
0x91
0x13
0x93
f
[0,1]
255
RESULT, 0
IORWF
100d
Execute
Q3
f,d
ffff
(dest)
destination
Write to
Q4
ffff
LCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
SUBROUTINE =
PC
PC
Q1
Long Call
[ label ]
0
PC + 1
k
None
LCALL allows an unconditional subrou-
tine call to anywhere within the 64k pro-
gram memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
1
2
MOVLW
MOVPF
LCALL
literal 'k'
Read
NOP
1011
Q2
=
=
k
PCL, (PCLATH)
255
16-bit Address
?
Address (SUBROUTINE)
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
PIC17C4X
LCALL
TOS;
0111
Execute
Execute
Q3
DS30412C-page 125
k
kkkk
register PCL
PCH
Write
NOP
Q4
kkkk