PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 97

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

13.4
The synchronous slave mode differs from the master
mode in the fact that the shift clock is supplied exter-
nally at the RA5/TX/CK pin (instead of being supplied
internally in the master mode). This allows the device
to transfer or receive data in the SLEEP mode. The
slave
CSRC (TXSTA<7>) bit.
13.4.1
The operation of the sync master and slave modes are
identical except in the case of the SLEEP mode.
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will trans-
mit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to interrupt vector
(0020h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
1996 Microchip Technology Inc.
Note:
Enable the synchronous slave serial port by set-
ting the SYNC and SPEN bits and clearing the
CSRC bit.
Clear the CREN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to TXREG.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
mode
USART Synchronous Slave Mode
USART SYNCHRONOUS SLAVE
TRANSMIT
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
re-enabled.
proper
is
entered
state
when
by
clearing
transmit
the
is
13.4.2
Operation of the synchronous master and slave modes
are identical except in the case of the SLEEP mode.
Also, SREN is a don't care in slave mode.
If receive is enabled (CREN) prior to the SLEEP instruc-
tion, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
Note:
Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
To enable reception, set the CREN bit.
The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
the CREN bit.
USART SYNCHRONOUS SLAVE
RECEPTION
To abort reception, either clear the SPEN
bit, the SREN bit (when in single receive
mode), or the CREN bit (when in continu-
ous receive mode). This will reset the
receive logic, so that it will be in the proper
state when receive is re-enabled.
PIC17C4X
DS30412C-page 97