MT9074 Mitel Networks Corporation, MT9074 Datasheet
MT9074
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MT9074 Summary of contents
Page 1
... The LIU interfaces the framer to T1 (T1 mode) or PCM 30 (E1 mode) transformer-isolated four-wire line with minimal external components required mode the MT9074 supports D4, ESF and SLC- 96 formats, meeting the latest recommendations including ITU I.431, AT&T PUB43801, TR-62411, ANSI T1.102, T1.403 and T1.408 mode the MT9074 Recommendations including G ...
Page 2
... MT9074 CS RESET IRQ VSS IC INT/MOT VDD R/W/WR AC0 RESET IRQ VSS IC 92 INT/MOT VDD R/W/WR AC0 100 PIN PLCC ...
Page 3
... RESET RESET (Input). This active low input puts the MT9074 in a reset condition. RESET should be set to high for normal operation. The MT9074 should be reset after power-up. The RESET pin must be held low for a minimum of 1 sec. to reset the device properly. 12 ...
Page 4
... D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading data from the MT9074. When low, the parallel processor is writing data to the MT9074. For Intel mode (WR), this active low write strobe configures the data bus lines as output. ...
Page 5
... C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and transmit serial PCM data of the MT9074. In the free-run (S/FR=0) or line synchronous mode (S/FR=1 and BS/LS=0) this signal is an output, while in bus synchronous mode (S/FR=1) this signal is an input clock which is phase- locked to the extracted clock (E1 ...
Page 6
... S/FR/C1.5i Sychronous/Freerun Extracted Clock (Input): If low, and the internal LIU is enabled, the MT9074 is in free run mode. Pins 45 C4b and 46 F0b are outputs generating system clocks. Slips will occur in the receive slip buffer as a result of any deviation between the MT9074's internal PLL (which is free - running) and the frequency of the incoming line data ...
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... Advance Information To accommodate some special applications, the MT9074 also supports a digital framer only mode by providing direct access to the transmit and receive data in digital format, i.e. by-passing the analog LIU front-end. The digital portion of the MT9074 connects selected channels of an incoming stream of time multiplexed 2 ...
Page 8
... The jitter tolerance of the clock extractor circuit exceeds the requirements of TR 62411 in T1 mode (see Figure 3) and G.823 in E1 mode (see Figure 4). Transmitter The transmit portion of the MT9074 LIU consists of a high speed digital-to-analog complementary line drivers. ...
Page 9
... Table 1 - Transmit Line Build Out (T1 1 1:1 100 Figure 5 - Analog Line Interface (T1) MT9074 Jitter Frequency (log scale) Line Build Out 0 to 133 feet 133 to 266 feet 266 to 399 feet 399 to 533 feet 533 to 655 feet -7.5 dB -15 dB -22.5 dB Fuse ...
Page 10
... MT9074 Name TX2-0 Transmit pulse amplitude. Select the TX2 –TX0 bits according to the line type, value of termination resistors (RT), and transformer turns ratio used TX2 TX1 TX0 After reset these bits are zero. 0.68uF ...
Page 11
... Table 3 - Maximum Curve for Figure 7 -499 -149 -149 -97 0 -.77 -.23 -.23 -.15 0 -.05 -. .95 Table 4 - Minimum curve for Figure 7 MT9074 0 175 220 499 752 0 .27 .34 .77 1.16 1.05 1.05 -.05 .05 .05 97 149 149 298 395 .15 .23 .23 .46 .61 .9 ...
Page 12
... Mhz Clock The MT9074 requires a 20 Mhz clock. This may provided ppm oscillator as per Figure 9. 20MHz OSC1 OUT OSC2 ( ) open Figure 9 - Clock Oscillator Circuit Alternatively, a crystal oscillator may be used. A complete oscillator circuit made crystal, resistors and capacitors is shown in Figure 10. The crystal specifi ...
Page 13
... Figure 11- TR 62411 Jitter Attenuation Curve Phase Lock Loop (PLL) The MT9074 contains a PLL, which can be locked to either an input 4.096 Mhz clock or the extracted line clock.The PLL will attenuate jitter from less than 2.5 Hz and roll-off at a rate of 20 dB/decade. Its intrinsic jitter is less than 0.02 UI. The PLL will meet the jitter transfer characteristics as specifi ...
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... DS1 payload only the first 24 time slots and the last (time slot 31, for the overhead bit ST-BUS are used (see Table 6). All unused channels are tristate. When signalling information is written to the MT9074 in T1 mode using ST-BUS control links (as opposed to direct writes by the microport to the on - board ...
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... The protocol appropriate for the application is selected via the Framing Mode Selection Word, address 10H of Master Control page mode MT9074 is capable of generating the overhead bit framing pattern and (for ESF links) the CRC remainder for transmission onto the DS1 trunk. The ...
Page 16
... MT9074 Frame # Ft Fs Notes Frame # Digital Interface ...
Page 17
... A maintenance channel or data link at 4,8,12,16,or 20 kHz for selected Sa bits is provided by the MT9074 in E1 mode to implement these functions. Note that for simplicity all Sa bits including Sa4 are collectively called national bits throughout this document. Bit three (designated as “A”), the Remote Alarm ...
Page 18
... TE control bit. When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU- T G.704. Table 12 outlines the operation of the AUTC, ARAI and TALM control bits of the MT9074. CAS Signalling Multiframing in E1 mode The purpose of the signalling multiframing algorithm is to provide a scheme that will allow the association of a specifi ...
Page 19
... MOT low) or Intel style control signals (by setting pin INT/MOT high). Control and Status Register Access The controlling microprocessor gains access to specific registers of the MT9074 through a two step process. First, writing to the Command/Address Register (CAR) selects one of the 15 pages of control and status registers (CAR address: AC4 = 0, AC3-AC0 = don't care, CAR data page number) ...
Page 20
... Table 10 Time slot to Channel Relationship. Reset Operation (Initialization) The MT9074 can be reset using the hardware RESET pin (see pin description for external reset circuit requirements) for T1 and (pin 11 in PLCC, pin 84 in MQFP) or the software reset bit RST (page 1H, address 1AH) for E1/T1 ...
Page 21
... Advance Information Data Link Operation Data Link Operation in E1 mode In E1 mode MT9074 has a user defined kbit/s data link for transport of maintenance and performance monitoring information across the PCM 30 link. This channel functions using the the PCM 30 timeslot zero non-frame ...
Page 22
... MT9074 Octet # Table 16 - Message Oriented Performance Report Structure (T1.403 and T1.408) Note: ADDRESS INTERPRETATION 00111000 SAPI = 14, C (CI 00111010 SAPI = 14, C/R = 1(Carrier ...
Page 23
... Interrupt Mask Word Three - page 1H, address 1EH) may occur. Dual HDLC MT9074 has two embedded HDLC controllers (HDLC0, HDLC1) each of which includes the following features: • Independent transmit and receive FIFO's; ...
Page 24
... MT9074 N bytes of data. The HDLC does not distinguish between the control and information fields and a packet does not need to contain an information field to be valid. The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the CRC-CCITT ...
Page 25
... Advance Information well as a receive to transmit loopback are also supported. Transmit and receive bit rates and enables can operate independently. In MT9074 the transceiver can operate at a continuous rate independent of RXcen and TXcen (free run mode) by setting the Frun bit of Control Register 1. ...
Page 26
... MT9074 flag followed by the data and closing flag is sent and zero insertion still included, but no CRC. That is, the FCS is injected by the microprocessor as part of the data field. This is used in V.120 terminal adaptation for synchronous protocol sensitive UI frames. HDLC Receiver After initialization and enabling, the receiver clocks in serial data, continuously checking for Go-aheads (0 1111 1110), fl ...
Page 27
... Slip Buffers Slip Buffer in T1 mode In T1 mode MT9074 contains two sets of slip buffers, one on the transmit side, and one on the receive side. Both sides may perform a controlled slip. The mechanisms that govern the slip function are a ...
Page 28
... In E1 mode in addition to the elastic buffer in the jitter attenuator(JA), another elastic buffer (two frames deep) is present, attached between the receive side and the ST-BUS (or GCI Bus) side of the MT9074 in E1 mode. This elastic buffer is configured as a slip buffer which absorbs wander and low frequency jitter in multi-trunk applications ...
Page 29
... Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9074 will allow a maximum of 26 channels (208 UI, unit intervals) of wander and low frequency jitter before a frame slip will occur. Write ...
Page 30
... UI. Framing Algorithm Frame Alignment in T1 Mode In T1 mode MT9074 will synchronize to DS1 lines formatted with either the D4 or ESF protocol. In either mode the framer maintains a running 3 bit history of received data for each of the candidate bit positions ...
Page 31
... The MT9074 will automatically force a reframe, if three consecutive frame alignment patterns or three consecutive non-frame alignment bits are in error. T1 Mode The MT9074 will automatically force a reframe if the framing bit error density exceeds the threshold programmed by control bits RS1-0 (Framing Mode Select Word page 1H, address 10H). RS1 = RS0 = 0 forces a reframe for 2 errors out of a sliding window of 4 framing bits ...
Page 32
... MT9074 >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe alignment CRC-to-CRC interworking. Re-align to new basic frame alignment. Start CRC-4 processing. E-bits set as per G ...
Page 33
... MT9074 Channel Signaling Channel Signaling in T1 mode In T1 mode,when control bit RBEn (page 1H, address 14H) is low the MT9074 will insert ABCD or AB signaling bits into bit 8 of every transmit DS0 channel every 6th frame. The AB or ABCD signaling bits from received frames 6 and 12 (AB) or from frames 6, 12, 18 and 24 (ABCD) will be loaded into an internal storage ram ...
Page 34
... Per Time Slot Control Words, pages 7H and 8H. Performance Monitoring Error Counters mode, MT9074 has eight error counters, which DS1 can be used for maintenance testing, an ongoing measure of the quality of a DS1 link and to assist the designer in meeting specifications such as TR62411 and T1 ...
Page 35
... In E1 mode, MT9074 has six error counters, which can be used for maintenance testing, an ongoing measure of the quality of a PCM 30 link and to assist the designer in meeting specifi ...
Page 36
... BPVO (page 01H, address 1DH) is initiated when the counter changes from FFFFH to 0000H. CRC-4 Error Counter (CC9-0) CRC-4 errors are counted by the MT9074 in order to support compliance with ITU-T requirements. This ten bit counter is located on page 04H, addresses 18H and 19H in E1 mode incremented by single error events, which is a maximum rate of twice per CRC-4 multiframe ...
Page 37
... This counter is located on page 04H, address 11H. Error Insertion In T1 mode MT9074 has six types of error conditions can be inserted into the transmit DS1 data stream through control bits, which are located on page 1, address 19H - Error Insertion Word. These error ...
Page 38
... MT9074 Digital Milliwatt If the control bit ADSEQ is one, a digital milliwatt sequence (Table 18 mode or (Table 19 mode may be transmit on any combination of selected channels. The channels are selected by setting bit three (TTST), in the Per Time Slot Control Word. Under the same control condition (ADSEQ equal to ...
Page 39
... It will toggle upon detection of 16 consecutive zeros on the line data there are less than N ones in a window of 8(N+1) bits - where 23. Timer Outputs In T1 mode MT9074 has a one second timer derived from the 20 Mhz oscillator pins. The timer may be used made to function performance messaging ...
Page 40
... This function can also be accomplished by toggling the INTA bit (page 1, address 1AH). All the interrupts of the MT9074 in T1 and E1 mode are maskable. This is accomplished through interrupt mask words zero to three, which are located on page 1, addresses 1BH to 1EH and the (optional) HDLC interrupt mask located at address 16 of page B ...
Page 41
... Advance Information Digital Framer Mode T1 mode Setting bit 4 in the Configuration Control Word (address 10H of Master Control Page 2) disables the LIU and converts the MT9074 into a digital T1 transceiver. The digital 2.048 backplane maps into transmit and receive digital 1.544 Mb/s streams. The 1.544 Mb/s transmit ...
Page 42
... MT9074 Control and Status Registers T1 Mode Master Control 1 (Page 01H) (T1) Address ( 10H (Table 21) Framing Mode Select 11H (Table 22) Transmit Alarm Control Word 12H (Table 23) Data Link Control Word 13H (Table 24) Transmit Bit Oriented Message 14H (Table 25) ...
Page 43
... Frame 1 6 frames after 0 Table 21 - Framing Mode Select (T1) MT9074 Name Functional Description FSI Fs Bit Include. Only applicable in D4 mode (not ESF or SLC96). Setting this bit causes errored Fs bits to be included as framing bit errors. A bad Fs bit will increment the Framing Error ...
Page 44
... MT9074 Bit Name Functional Description 7 ESFYEL ESFYellow Alarm. Setting this bit while in ESF mode causes a repeating pattern of eight 1’s followed by eight 0’ insert onto the transmit FDL (JTS bit set low - see Data Link Control Word) or sixteen 1’s (Japan Telecom bit set high) ...
Page 45
... SM1-0 Signalling Message. These two bits are used to fill the vacant bit positions available on CSTo when the MT9074 is operating trunk. The first two bits of each reporting nibble of CSTo contain the AB signalling bits. The last two contain SM1 and SM0 (in that order) ...
Page 46
... PLBK Payload Loopback. If one, all time slots received on RTIP/ RRING are connected to TTIP/ TRING on the ST-BUS side of the MT9074. If zero, this feature is disabled. If receive robbed bit signaling data included in the looped data, then the control bit RBEn (Page 1 Address 14H, ...
Page 47
... Fs bits (in D4 mode only). A one, zero or one-to-zero transition has no function. 3 LOSE Loss of Signal Error Insertion. If one, the MT9074 transmits an all zeros signal (no pulses). Zero code suppression is overridden. If zero, data is transmitted normally. 2 PERR Payload Error Insertion. A zero - ...
Page 48
... MT9074 Bit Name Functional Description 2 EXTOSC External Oscillator Setting this bit connects the pin OSC1 to a TTL compatible input. This allows for a system design employing a TTL output oscillator as a 20.000 Mhz reference clock. 1 RSV Reserved. Set to zero for normal operation. 0 RSV Reserved ...
Page 49
... When an interrupt Error Counter error counter 0 Table 34 - Interrupt Mask Word Two (T1) MT9074 Name Functional Description OOFOM Out Of Frame Overflow Interrupt Mask. When unmasked an interrupt is initiated whenever the out of frame counter changes state from changes from FFH to 00H unmasked masked ...
Page 50
... A one sets the MT9074 to accept a unipolar NRZ format input stream on RxA as the line input, and to transmit a unipolar NRZ format stream on TxB. A zero causes the MT9074 to accept a complementary pair of dual rail inputs on RxA/RxB and to transmit a complementary pair of dual rail outputs on TxA/TxB. ...
Page 51
... Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. CP6-0 CP6-0 CP6-0 CP6-0 Table 37 - Master Control 2 (Page 02H) (T1) MT9074 Names 51 ...
Page 52
... MT9074 Bit Name Functional Description 7 T1/E1 T1/E1 mode selection. when this bit is zero, the device mode. When set high, the device mode. 6-5 RSV Reserved. Must be kept at 0 for normal operation. 4 LIUEn LIU Enable. Setting this bit low enables the internal LIU front-end. ...
Page 53
... Table 42 - Custom Pulse Word 3 (Page 2, Address 1EH) (T1) Bit Name 7 6-0 CP6-0 Custom Pulse. These bits provide the programming the programming the MT9074 Functional Description RSV Reserved. Must be kept at 0 for normal operation. capability for programming magnitude setting for the TTIP/TRING line driver A/D converter during the fourth phase of a mark ...
Page 54
... MT9074 Master Status 1 (Page03H) (T1) Address ( 10H (Table 45) Synchronization Status Word 11H (Table 46) Alarm Status Word 12H (Table 47) Timer Status Word 13H (Table 48) Most Significant Phase Status Word 14H (Table 49) Least Significant Phase Status Word 15H (Table 50) ...
Page 55
... D4Y48 Synchronization. 5 SECYEL 4 ESFYEL framing bits MT9074 Name Functional Description D4 Yellow Alarm millisecond sample. This bit is set if bit position 2 of virtually every DS0 channel is a zero for a period of 48 milliseconds. The alarm is tolerant of errors by permitting ones in the integration period. This bit is updated every 48 milliseconds ...
Page 56
... MT9074 Bit Name Functional Description 7 1SEC One Second Timer Status. This bit changes state once every 0.5 seconds. 6 2SEC Two Second Timer Status. This bit changes state once every second and is synchronous with the 1SEC timer. 5 5SEC Five Second Timer Status. This bit changes state once every 2 ...
Page 57
... STBUS bit times there are between the transmit elastic buffer STBUS write frame boundary and the internal read frame boundary. The count is updated every 250 uS. (Page 3, Address 18H) (T1) Functional Description ID7-0 ID Number. Contains device code 10101111 Table 54 - Identification Word (Page 3, Address 1FH) (T1) MT9074 57 ...
Page 58
... MT9074 Master Status 2 (Page04H)(T1) Address ( 10H (Table 56) PRBS Error Counter 11H (Table 57) CRC Multiframe counter for PRBS 12H (Table 58) Alarm Reporting Latch 13H (Table 59) Framing Bit Counter 14H (Table 60) Out of Frame / Change of Frame Alignment Counters 15H (Table 61) ...
Page 59
... In ESF mode the ESF framing bits are monitored mode Fs bits may be monitored as well as Ft bits. See - Section 15.5 Framing Bit Counter. The count is only active if the MT9074 is in synchronization. Table 59 - Framing Bit Counter (Page 4, Address 13H) (T1) (48 Alarm 59 ...
Page 60
... MT9074 Bit Name Functional Description OOF3 - 0 Out Of Frame Counter. This four bit counter is incremented with every loss synchronization COFA3 - 0 Change of Frame Alignment Counter. This four bit counter is incremented resynchronization is done which results in a shift in the frame alignment position. Table 60 - Out Of Frame / Change of Frame ...
Page 61
... BPVI 2 PRBSI Psuedo 1 PDVI Pulse Density Violation Interrupt MT9074 Functional Description Framing Bit Error Interrupt. When unmasked this interrupt bit goes high whenever an erroneous framing bit is detected (provided the circuit is in terminal frame sync). Reading this register clears this bit. Error Interrupt ...
Page 62
... MT9074 Bit Name Functional Description 7 FEO Framing Bit Error Counter Overflow unmasked this interrupt bit goes high framing changes from FFH to 00H. Reading this register clears this bit. 6 CRCO CRC-6 Overflow unmasked this interrupt bit goes high whenever the CRC-6 error counter changes from FFH to 00H ...
Page 63
... Reading this register clears this bit. Table 69 - Interrupt Word Three (Page 4, Address 1EH) (T1) Bit 1 DS1 channel 24 0 MT9074 Name Functional Description BIOMI Bit Oriented Message Interrupt. When unmasked this interrupt bit goes high whenever a pattern 111111110xxxxxx0 received on the FDL that is different from the last message. ...
Page 64
... MT9074 Bit Name Functional Description 7 FEOL Framing Counter Overflow Latch. This bit is set when the framing overflows cleared after being read. 6 CRCOL CRC-6 Overflow Latch. This bit is set when the crc error counter overflows cleared after being read. 5 OOFOL Out Of Frame Counter Overflow Latch ...
Page 65
... RPSIG bit is low. Table 71 describes the bit allocation within each of the 24 active ST-BUS time slots of CSTi Functional Description MT9074 ...
Page 66
... MT9074 Bit Name A(n), Transmit Signalling Bits for Channel n. When control bit MSN = 1 and RPSIG = 1 this nibble is used. For ESF links these 4 bits are transmitted on the associated B(n) DS1 channel (see table 8) in frames 6, 12, 18 and 24. For D4 links bits A are C(n), transmit on the associated DS1 channel of frame 6 and bits B are transmit on the D(n) associated DS1 channel of frame 12 ...
Page 67
... If one, the channel will MT9074 Name Functional Description RPSIG Serial Signaling Enable. If set low, the transmit signaling buffer for the equivalent DS1 channel will be sourced from the ST-BUS channel on CSTi associated with it. If set high the transmit signaling RAM must be programmed via the microport ...
Page 68
... MT9074 Per Channel Receive Signalling (T1 and E1 mode) (Pages 9 and 0AH) Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive Signalling Control Words for DS1 channels and respectively. Table 76 illustrates the mapping between the addresses of these pages and the DS1 channel numbers. Table 77 describes bit allocation within each of these registers ...
Page 69
... SYNIM, MFSYIM, CSYNIM, AISIM, LOSIM, CEFIM, YIM, SLPIM FERIM, CRCIM, EBIM, AIS16IM, BPVIM, PRBSIM, AUXPIM & RAI FEOM, CRCOM, EOM, BPVOM, PRBSOM, PRBSMFO JAIM,1SECIM, 5SECIM, RCRIM, SIGIM NRZUNI, REDBL, REMID, REMAX Table 78 - Master Control 1 (Page 1) (E1) MT9074 Function SPND, INTA, CNTCLR, SAMPLE, 69 ...
Page 70
... REFRM bit. MFRF Multiframe Reframe. If one, for at least one frame, and then cleared the MT9074 will initiate a search for a new signalling multiframe position. Reframing function is activated on the one to zero transition of the MFRM bit. (Page 1, Address 10H) ...
Page 71
... DSTo with an arbitrary alignment. When zero, the receive operates normally. 2 TxTRSP Transmit Transparent Mode. If one, the MT9074 is in transmit transparent mode. No framing or signaling is imposed on the data transmit from DSTi onto the line. If zero termination mode. 1 TIU1 Transmit International Use One. ...
Page 72
... MT9074 Bit Name Functional Description 1- 0 X2, X3 These bits are transmitted on the PCM 30 2048 kbit/sec. link in bit positions seven respectively, of time slot 16 of frame zero of every multiframe. X2 and X3 are normally set to one. If receive channel 16 data included in the looped data then the control bit TxCCS (Page, ...
Page 73
... RLBK Remote Loopback. If one, then all bipolar data received on RRTIP/ RRING are directly routed to TTIP/ TRING on the PCM 30 side of the MT9074. If zero, then this feature is disabled. 1 SLBK ST-BUS Loopback. If one, then all time slots of DSTi are connected to DSTo on the ST-BUS side of the MT9074 ...
Page 74
... PCM 30 data. A one, zero, or one to zero transition has no function. LOSE Loss of Signal Error Insertion. If one, the MT9074 transmits an all zeros signal (no pulses) in every PCM 30 time slot. When HDB3 encoding is activated no violations are transmitted. If zero, data is transmitted normally. ...
Page 75
... LOSIM (status page 3 2 CEFIM Table 90 - Interrupt Mask Word Zero (E1) MT9074 Name Functional Description Synchronization Mask. When unmasked (SYNI=1) an interrupt is initiated whenever change of state of basic frame synchronization condition exists unmasked masked. Multiframe Synchronization Interrupt Mask. When unmasked ...
Page 76
... MT9074 Bit Name Functional Description 1 YIM Remote Signalling Multiframe Alarm Interrupt Mask. When unmasked (YI=1), an interrupt is initiated whenever a change of state of multiframe received unmasked masked. 0 SLPIM SLIP Interrupt unmasked (SLPI=1), an interrupt is initiated when a controlled frame slip unmasked masked. Table 90 - Interrupt Mask Word Zero (E1) ...
Page 77
... Name Overflow 0 SIGIM Table 93 - Interrupt Mask Word Three (E1) Interrupt When whenever the Mask. When MT9074 Functional Description Signalling (CAS) Interrupt Mask. When unmasked and any of the receive ABCD bits of any channel changes state an interrupt is initiated unmasked masked. (Page 1, Address 1EH) 77 ...
Page 78
... A one sets the MT9074 to accept a unipolar NRZ format input stream on RxA as the line input, and to transmit a unipolar NRZ format stream on TxB. A zero causes the MT9074 to accept a complementary pair of dual rail inputs on RxA/RxB and to transmit a complementary pair of dual rail outputs on TxA/TxB. ...
Page 79
... Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. CP6-0 CP6-0 CP6-0 CP6-0 Table 95 -Master Control 2 (Page 02H) (E1) MT9074 Names 79 ...
Page 80
... MT9074 Bit Name Functional Description 7 T1/E1 E1 mode selection. when this bit is one, the device mode. 6-5 RSV Reserved. Must be kept at 0 for normal operation. 4 LIUEn LIU Enable.Setting this bit low enables the internal LIU front-end. Setting this pin high disables the LIU ...
Page 81
... Name 7 6-0 CP6-0 Custom Pulse. These bits provide the programming the programming the for the TTIP/ MT9074 Functional Description RSV Reserved. Must be kept at 0 for normal operation. capability for programming magnitude setting for the TTIP/TRING line driver A/D converter during the fourth phase of a mark. The greater ...
Page 82
... MT9074 Master Status 1 (Page03H) (E1) Address ( 10H (Table 103) Synchronization Status Word 11H (Table 104) Alarm Status Word 1 12H (Table 105) Timer Status Word 13H (Table 106) Most Significant Phase Status Word 14H (Table 107) Least Significant Phase Status Word ...
Page 83
... LOSS CRCIWK 3 AIS16S 2 AISS Table 104 - Alarm Status Word 1 (Page 3, Address 11H) (continued) (E1) MT9074 Functional Description Receive CRC Error Status One. If one, the evaluation of the last received submultiframe 1 resulted in an error. If zero, the last submultiframe 1 was error free. Updated on a submultiframe 1 basis ...
Page 84
... This bit shall be low when T2 becomes high. Refer to I.431 Section 5.9.2.2.3. T2 Timer Two. This bit will be high when the MT9074 acquires terminal frame synchronization persisting for 10 msec. This bit shall be low when non-normal operational frames are received. I.431 Section 5.9.2.2.3. ...
Page 85
... Table 107 - Least Significant Phase Status Word Bit 7 6-0 RFA2-8 Receive Frame Alignment Signal Errored Frame Table 108 - Receive Frame Alignment Signal MT9074 Name Functional Description counter that indicates the number of time slots between the receive elastic buffer internal write frame boundary and the ST-BUS read frame boundary ...
Page 86
... MT9074 Bit Name Functional Description 7 - PD4 - Peak Detector 3 PD0 These five bits indicate the level of the received signal AMI pulses. PD4 PD3 PD2 PD1 PD0 LLOS LIU Loss of Signal indication. This ...
Page 87
... Receive Slip Status. A change of state (i.e., 1-to-0 or 0-to-1) indicates that controlled frame occurred Unused. Table 113 - Alarm Status Word 2 (Page 3, Address 1BH) (E1) Name Functional Description ID7-0 ID Number. Contains device code 10101111 Table 114 - Identification Word (Page 3, Address 1FH) (E1) MT9074 bit a receive slip has 87 ...
Page 88
... MT9074 Master Status 2 (Page-4) Master Status 2 (Page 04H) (E1) Address ( 10H (Table 116) PRBS Error Counter 11H (Table 117) CRC Multiframe counter for PRBS 12H (Table 118) Alarm Reporting Latch 13H (Table 119) Framing Bit Counter 14H (Table 120) ...
Page 89
... RSLIP Received Slip. This bit is set to one 0 Bit EFAS7 - 0 Errored FAS Counter bit Table 119 - Errored Frame Alignment Signal MT9074 Functional Description RAI Remote Alarm Indication. This bit is set to one in the event of receipt of a remote alarm, i.e. A(RAI cleared when the register is read. ...
Page 90
... MT9074 Bit Name Functional Description 7 Unused 1-0 EC9-8 E bit Error Counter. The most significant 2 bits of the E bit error counter. Table 120 - E-bit Error Counter (Page 4, Address 14H) (E1) Bit Name Functional Description EC7-0 E bit Error Counter. The least significant 8 bits of the E-bit error counter ...
Page 91
... Remote alarm Interrupt. When unmasked this interrupt bit goes high whenever the bit 3 of non-frame alignment signal is high. Reading this register clears this bit. Table 127 - Interrupt Word One (Page 4, Address 1CH) (E1) MT9074 Alignment goes high this register Signal this Alarm ...
Page 92
... MT9074 Bit Name Functional Description 7 FERRO Errored Framing Signal Counter Interrupt. When unmasked this interrupt bit goes high whenever the errored frame alignment signal counter changes from FFH to 00H. Reading this register clears this bit. 6 CRCO CRC Error Counter Overflow Interrupt. When unmasked this ...
Page 93
... Pseudo Random Bit Sequence FOFOL Multiframe Counter Latch. This bit is set when the multiframe counter attached to the PRBS error counter overflows cleared after being read Unused. Table 130 - Overflow Reporting Latch (Page 4, Address 1FH) (E1) Counter Overflow Counter Overflow MT9074 93 ...
Page 94
... MT9074 Per Channel Transmit Signalling (Pages 5 and 6) (E1) Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit Signalling Control Words for Channel Associated Signalling (CAS) channels and respectively. Table 132 illustrates the mapping between the addresses of these pages and the CAS channel numbers. ...
Page 95
... Timeslots Table 134 - Mapping to CEPT Channels(Page 8H and 9H) (E1) Functional Description MT9074 ...
Page 96
... MT9074 Bit Name 7 TXMSG Transmit Message Mode. if high, the data from the corresponding address location of Tx message mode buffer is transmitted in the corresponding PCM 30 time slot. If zero, the data on DSTI is transmitted on the corresponding PCM 30 time slot. 6 ADI Alternate Digit Inversion. If one, the corresponding transmit time slot data on DSTI has every second bit inverted ...
Page 97
... Table 138 - Receive CAS Channels (CSTo) (E1 Functional Description Functional Description MT9074 ...
Page 98
... MT9074 HDLC Control and Status (Page B for HDLC0 and Page C for HDLC1) Address Control (Write/Verify) 10H(Table 140) Address Recognition 1 11H(Table 141) Address Recognition 2 12H (Table TX FIFO 142/143) 13H(Table 144) HDLC Control 1 14H(Table 145) --- 15H(Table 146) HDLC Control 2 16H(Table 147) Interrupt Mask ...
Page 99
... Name BIT7-0 This is the received data byte read for single byte Table 143 - RX FIFO Read Register Comparison MT9074 Functional Description two status bits from the control register 1 (EOP and FA), and the resulting 10 bit word is written to the TX FIFO. The FIFO status ...
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... MT9074 Bit Name Functional Description 7 ADREC When high this bit will enable address forces the receiver to recognize only those packets having the unique address as programmed in the Recognition Registers or if the address is an All call address. 6 RxEN When low this bit will disable ...
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... RX FIFO empty 0 1 The number of bytes in the RX FIFO is less than the interrupt threshold level FIFO full The number of bytes in the RX FIFO has reached or exceeded the interrupt threshold level. Table 145 - HDLC Status Register (Page B & C Address 14H) MT9074 101 ...
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... MT9074 Bit Name Functional Description 7 INTSEL Interrupt Selection. When high, this bit will cause bit 2 of the Interrupt Register to reflect a TX FIFO underrun (TXunder). When low, this interrupt will reflect a frame abort (FA). 6 CYCLE Cycle. When high, this bit will cause ...
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... These bits are as the transmitter sent them; that is, most significant bit first and inverted. This register is updated at the end of each received packet and therefore should be read when end of packet is detected. Table 150 - Receive CRC LSB Register (Page B & C, Address 19H) MT9074 103 ...
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... MT9074 Bit Name Functional Description 7- TxCNT Transmit Byte Count Register. The 0s 7-0 Transmit Byte indicating the length of the packet about to be transmitted. When this register reaches the count of one, the next write to the Tx FIFO will be tagged as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO ...
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... Full Status Level Table 154 - HDLC Control Register 3 (Page B & C, Address 1DH) MT9074 112 128 112 128 105 ...
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... MT9074 Bit Name Functional Description 7 --- Unused. 6-4 RFFS2-0 These bits select the RXFF (Rx FIFO Full) interrupt threshold level: RFF RFF RFF --- Unused. 2-0 TFLS2-0 These bits select the TXFL (Tx FIFO ...
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... Voltages are with respect to ground (V ‡ Sym Min Typ 2 2 MT9074 ) unless otherwise stated. Min Max -0 -65 150 ) unless otherwise stated. SS Units Test Conditions 85 ˚ unless otherwise stated. SS Max Units ...
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... MT9074 AC Electrical Characteristics -Timing Parameter Measurement Voltage Levels Characteristics 1 TTL Threshold Voltage 2 CMOS Threshold Voltage 3 Rise/Fall Threshold Voltage High 4 Rise/Fall Threshold Voltage Low Note 1: Timing for output signals is based on the worst case result of the combination of TTL and CMOS thresholds. AC Electrical Characteristics ...
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... Typ t 70 RDL t 60 RDH t 0 CSS t 0 CSH t 10 ADS t 15 ADH t 90 DDR t 90 DAZ t 15 DSW t 15 DHW MT9074 t CSH t RWH t ADH t DAZ DHR DHW DSW Max Units Test Conditions =150pF ...
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... MT9074 A0-A4 D0-D7 READ D0-D7 WRITE AC Electrical Characteristics - Transmit Data Link Timing (T1 mode) Characteristic 1 Data Link Clock Pulse Width 2 Data Link Setup 3 Data Link Hold TxDLCLK TxDL Figure 18 - Transmit Data Link Timing Diagram (T1 mode) 110 t CYC t RDL t RDH t CSS t ADS t DDR VALID DATA ...
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... Typ t 244 TDC t 35 TDS t 35 TDH t TDC t t DLH DLS Example kb/s Example kb/s Sym Min Typ t RDC t RDD t RFD MT9074 Max Units Test Conditions ns 150pF TT Max Units Test Conditions 160 ns 50pF 45 ns 50pF 45 ns ...
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... MT9074 RxFP RxDLCLK RxDL Figure 21 - Receive Data Link Functional Timing (T1 mode) RxFP t RFD E1.5o RxDLCLK t RDD RxDL Figure 22 - Receive Data Link Diagram (T1 mode) AC Electrical Characteristics - Receive Data Link Timing (E1 mode) Characteristic 1 Data Link Clock Output Delay 2 Data Link Output Delay 3 RxFP Output Delay ...
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... Example kb/s Example kb/s t RDC Sym Min Typ Max Units FPS t 70 FPL t 20 SIS t 20 SIH t 75 SOD t 40 FDP MT9074 TT TT, CT Test Conditions ns Line Synchronization Mode 150pF ns Line Synchronous Mode 113 ...
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... MT9074 ST-BUS Channel 31 Bit Cells Bit 0 F0b C4b Figure 25 - ST-BUS Functional Timing Diagram ST-BUS Bit Bit Cell Stream F0b (Input) C4b (Input) All Input Streams All Output Streams Figure 26 - ST-BUS Timing Diagram (Input Clocks) 114 Channel 0 Channel 0 Bit 7 Bit 6 Bit Cell ...
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... SIS SOD Sym Min Typ t MOD Frame Bit 4 Bit 0 Bit 7 Bit Cell 4WO 4WO TT, Max Units Test Conditions 50 ns 150pF 256 C2 periods -100nsec Frame 0 Bit 6 Bit 5 Bit 4 Bit 0 MT9074 V CT Bit 7 115 ...
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... MT9074 DSTi Bit 7 Bit 6 Bit 5 Bit Cells F0b C4b (4.096 MHz) TxMF Figure 29 - Transmit Multiframe Functional Timing (T1 mode or E1 mode) F0b t MOD C4b (1) RxMF t MS (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 30 - Multiframe Timing Diagram (T1 mode or E1 mode) ...
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... Receive Data Hold Time Sym Min Typ Max t 648 DW t 244 RDS RDH Sym Min Typ Max t 15 RDS t 15 RDH MT9074 Units Test Conditions ns 150pF - T1 mode ns 150pF - E1 mode ns Units Test Conditions ns ns 117 ...
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... MT9074 Frame Frame 12 1 Channel SBit Most Significant Bit (First) Frame Frame 15 0 Time Slot Most Significant Bit (First) Channel Channel 0 31 Most Significant Bit (First) 118 1.5 s • • • • • • • • Channel • • • • 125 s ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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