MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 35

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
Associated with each counter is a maskable event
occurrence interrupt and a maskable counter
overflow interrupt. Overflow interrupts are useful
when cumulative error counts are being recorded.
For example, every time the framing bit error counter
overflow interrupt (FERO) occurs, 256 frame errors
have been received since the last FERO (page 04H,
address 1DH)interrupt. All counters are cleared and
held low by programming the counter clear bit -
CNTCLR - high (bit 4 of the Reset Control Word,
page 1H, address 1AH). An alternative approach to
event reporting is to mask error events and to enable
the 1 second sample bit (SAMPLE - bit 3 of the
Reset Control Word). When this bit is set the
counters for change of frame alignment, loss of
frame alignment, bpv errors, crc errors, errored
framing bits, and multiframes out of sync are
updated on one second intervals coincident with the
maskable one second interrupt timer.
In E1 mode, MT9074 has six error counters, which
can be used for maintenance testing, an ongoing
measure of the quality of a PCM 30 link and to assist
the designer in meeting specifications such as ITU-T
I.431 and G.821. All counters can be preset or
cleared by writing to the appropriate locations.
Associated with each counter is a maskable event
occurrence interrupt and a maskable counter
overflow interrupt. Overflow interrupts are useful
when cumulative error counts are being recorded.
For example, every time the frame error counter
overflow (FERO) interrupt occurs, 256 frame errors
have been received since the last FERO interrupt. All
counters are cleared and held low by programming
the counter clear bit (master control page 01H,
address 1A, bit 4) high. Counter overflows set bits in
the counter overflow latch (page 04H, address 1FH);
this latch is cleared when read.
The overflow reporting latch (page 04H, address
1FH) contains a register whose bits are set when
individual counters overflow. These bits stay high
until the register is read.
T1 Counters
Framing Bit Error Counter (FC7-0)
This eight bit counter counts errors in the framing
pattern. In ESF mode any error in the 001011
framing pattern increments the counter. In SLC-96
mode any error in the Ft bit position is counted. In D4
mode Ft errors are always counted, Fs bits (except
for the Sbit in frame 12) may optionally be counted (if
control bit FSI is set high - page 1H, address 10H, bit
2). The counter is located on page 4H, address 13H.
There are two maskable interrupts associated with
the Framing bit error measurement. A single error
may generate an interrupt (enable by setting FERI
high - bit 7 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit FEOM high - bit 2 of
Interrupt Mask Word Two (page 1H, address 1DH).
Out Of Frame / Change Of Frame Alignment
Counter (OOF3-0/COFA3-0)
This register space is shared by two nibbles. One is
the count of out of frame events. The other
independent counter is incremented when, after a
resynchronization, the frame alignment has moved.
This count is reported in page 4, address 13H.
There are two interrupts associated with the Change
of Frame Alignment counter. A single error may
generate an interrupt (enable by setting COFAI high -
bit 4 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit COFAO high - bit 4 of
Interrupt Mask Word Two (page 1H, address 1DH).
There is one interrupt associated with the Out of
Frame counter. A counter overflow interrupt may be
enabled by setting control bit OOFO high - bit 5 of
Interrupt Mask Word Two (page 1H, address 1DH).
Multiframes out of Sync Counter (MFOOF7-
MFOOF0)
This eight bit counter MFOOF7 - MFOOF0 is located
on page 4 address 15H, and is incremented once per
multiframe (1.5 ms for D4 and 3 ms for ESF) during
the time that the framer is out of terminal frame
synchronization.
There is a maskable interrupt associated with the
measurement. A counter overflow interrupt may be
enabled by setting control bit MFOOFO high - bit 1 of
Interrupt Mask Word Two (page 1H, address 1DH).
CRC-6 Error Counter (CC15-0)
CRC-6 errors are recorded by this counter for ESF
links. This 16 bit counter is located on page 4H,
addresses 18H and 19H.
There are two maskable interrupts associated with
the CRC error measurement. A single error may
generate an interrupt (enable by setting CRCI high -
bit 6 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit CRCO high - bit 6 of
Interrupt Mask Word Two (page 1H, address 1DH).
MT9074
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