MT9075B Mitel Networks Corporation, MT9075B Datasheet
MT9075B
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MT9075B Summary of contents
Page 1
... HDLC controllers for S The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line. The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450 ...
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... MT9075B CS RESET IRQ VSS IC INT/MOT VDD R/W/WR AC0 RESET IRQ VSS IC INT/MOT 92 VDD R/W/WR AC0 100 PIN PLCC ...
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... RESET RESET (Input). This active low input puts the MT9075B in a reset condition. RESET should be set to high for normal operation. The MT9075B should be reset after power- up. The RESET pin must be held low for a minimum of 1 sec. to reset the device properly. 12 ...
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... In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading data from the MT9075B. When low, the microprocessor is writing data to the MT9075B. For Intel mode (WR), this active low write strobe configures the data bus lines as output ...
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... LOS Loss of Signal or Synchronization (Output). When high, and LOS/LOF (page 02H address 13H bit 2) is zero, this signal indicates that the receive portion of the MT9075B is either not detecting an incoming signal (bit LLOS on page 03H address 18H is one detecting a loss of basic frame alignment condition (bit SYNC on page 03H address 10H is one) ...
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... PCM 30 transmit signal BL/FR Bus or Line/Freerun (Input). If this pin is set to high, the MT9075B is in the System Bus or Line Synchronous mode depending on the BS/LS pin. If low, the MT9075B is in the free run mode VDD Positive Power Supply (Input) ...
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... ETS requirements. The MT9075B system timing may be slaved to the line, operated in freerun mode, or controlled by an external timing source. MT9075B mode, the ...
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... MT9075B Functional Description MT9075B Line Interface Unit (LIU) Receiver The receiver portion of the MT9075B LIU consists of an input signal peak detector, an optional two-stage equalizer, a smoothing filter, adaptive threshold comparators, data and clock slicers, and a clock extractor. Receive equalization gain can be set via ...
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... OSEC resistors are only Table 1 - Transformer Manufacturers and Part coax Timing Source The MT9075B can use either a clock or crystal, connecting to pins OSC1 and OSC2, as the reference timing source. Rx Figure 6 shows a 20MHz clock oscillator, with 50ppm tolerance, directly connected to the OSC1 pin of the MT9075B ...
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... JA will not attenuate jitter. To ensure normal operation, the JA FIFO depth should be set in software to be larger than the anticipated maximum UI of input jitter. Clock Jitter Attenuation Modes MT9075B has three basic jitter attenuation modes of operation, selected by the BS/LS and BL/FR control pins. • System Bus Synchronous Mode. ...
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... JA selection under certain modes. Table 2 shows the configuration of related control pins and control bits required to place the MT9075B in the appropriate jitter attenuation mode. Referring to the mode names given in Table 2, the basic operation of the jitter attenuation modes is summarized as follows: • ...
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... A maintenance channel or data link at 4,8,12,16,or 20 kHz for selected S bits is provided by the a MT9075B to implement these functions. Note that for simplicity all S bits including S a called national bits throughout this document. Bit three (designated as “A”), the Remote Alarm Indication (RAI), is used to indicate the near end basic frame synchronization status to the far end of a link ...
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... When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU-T G.704. Table 4 outlines the operation of the AUTC, ARAI and TALM control bits of the MT9075B. Description Automatic CRC-interworking is activated valid CRC MFAS is being received, transmit RAI will flicker high with every reframe (8 msec ...
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... The parallel port may be configured for Motorola style control signals (by setting pin INT/ MOT low) or Intel style control signals (by setting pin INT/MOT high). The controlling microprocessor gains access to specific registers of the MT9075B through a two step Page Address ...
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... Cleared Table 8 illustrates the organization of the MT9075B transmit and receive national bit buffers. Each row is an addressable byte of the MT9075B national bit buffer, and each column contains the national bits of an odd numbered frame of each CRC-4 Multiframe. The transmit and receive national bit buffers are located at page 0DH and 0EH respectively ...
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... DSTi data can be programmed using register 17H of page 01H to be sent transparently onto the line. Data Link Operation Timeslot 0 The MT9075B has a user defined kbit/s data link for transport of maintenance and performance monitoring information across the PCM 30 link. This channel functions using the S ...
Page 17
... Sequence (FCS) Data Transparency (Zero Insertion/Deletion) Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis MT9075B “01111110 ” (7EH). The transmitter 2 ...
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... MT9075B and inserted after all sequences of 5 contiguous 1s (including the last five bits of the FCS). Upon receiving five contiguous 1s within a frame the receiver deletes the following 0. Invalid Frames A frame is invalid if one of the following four conditions exists: • If the FCS pattern generated from the received data does not match the “ ...
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... In addition, seven bits of address comparison can be realized on the first byte if this is a single byte address by setting the Seven bit of Control Register 2 (address 15H). MT9075B injected by the When . ...
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... In addition to the elastic buffer in the jitter attenuator(JA), another elastic buffer (two frames deep) is present, attached between the receive side and the ST-BUS (or GCI Bus) side of the MT9075B. This elastic buffer is configured as a slip buffer which absorbs wander and low frequency jitter in multi- trunk applications ...
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... Read Pointer Figure 9 - Read and Write Pointers in the Slip Buffers Framing Algorithm The MT9075B contains three distinct framing algorithms: multiframe alignment. Figure state diagram that illustrates these algorithms and how they interact. After power-up, the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM 30 receive bit stream ...
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... MT9075B >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe alignment CRC-to-CRC interworking. Re-align to new basic frame alignment. Start CRC-4 processing. E-bits set as per G ...
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... CRC-4 multiframing search is complete. Channel Signalling When control bit TxCCS (page 01H, address 1AH) is set to one, the MT9075B is in Common Channel Signalling (CCS) mode. When TxCCS is low Channel Associated Signalling mode (CAS). The CAS mode ABCD signalling nibbles can be passed ...
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... DSTi System DSTo Error Counters Tx The MT9075B has nine error counters, which can be PCM30 Rx used for maintenance testing, an ongoing measure of the quality of a PCM 30 link and to assist the designer in meeting specifications such as ITU-T I.431 and G.821. All counters can be preset or cleared by writing to the appropriate locations. A separate status page - “ ...
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... This counter is located on page 04H, address 11H. E-bit Counter (EC9-0) E-bit errors are counted by the MT9075B in order to support compliance with ITU-T requirements. This ten bit counter is located on page 04H, addresses 13H and 14H respectively incremented by single error events, with a maximum rate of twice per CRC- 4 multiframe ...
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... MT9075B single error events, which is a maximum rate of twice per CRC-4 multiframe. There is a maskable interrupts associated with the CRC error measurement. CRCI (page 01H, address 1CH) is initiated when the least significant bit of the counter toggles, and CRCO (page 01H, address 1DH) is initiated when the counter overfl ...
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... The interrupt acknowledgment function can also be accomplished by toggling the INTA bit (page 01H, address 1AH). All the interrupts of the MT9075B are maskable. This is accomplished through the corresponding interrupt mask words on page 01H (except for the HDLC interrupt mask registers which are located on page 0BH and 0CH) ...
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... SLIP D7 00000100 National Use/ HDLC0 D7 00000010 Signalling/ HDLC1 D7 00000001 Table 11 - MT9075B Interrupt Vectors Preliminary Information Interrupt Description SYNI - Loss of Synchronization. D0 MFSYI - Loss of Multiframe Sync. CSYNI - Loss of CRC-4 Sync Remote Multiframe Sync. Fail. RAII - Remote Alarm Indication. AISI - Alarm Indication Signal. D0 AIS16I - AIS on Channel 16. ...
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... SYNI, RAII, AISI, AIS16I, LOSI, FERI, BPVO & SLPI EBI, CRCI, CEFI, BPVI, RCR0I, RCR1I, BERI & SIGI EBOI, CRCOI, CALNI, FEROI, JAI, BEROI, AUXPI & CMFOI MFSYI, CSYNI, YI, 1SECI, T1I, T2I CTXP, LL0, LL1, LL2 Table 12 - Master Control 1 (Page 01H) MT9075B Names - nibI,S bitI,C8S ...
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... MT9075B Bit Name Functional Description 7 ASEL AIS Select. This bit selects the criteria on which the detection of a (0) valid Alarm Indication Signal (AIS) is based. If zero, the criteria is less than three zeros in a two frame period (512 bits). If one, the criteria is less than three zeros in each of ...
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... Preliminary Information 2 TxTRSP Transmit Transparent Mode. If one, the MT9075B is in transmit (0) transparent mode. No framing or signaling is imposed on the data transmit from DSTi onto the line. If zero termination mode. 1 CSYN CRC-4 Synchronization. If zero, basic CRC-4 (0) processing is activated, and TIU0 bit and TIU1 bit programming will be overwritten ...
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... MT9075B Bit Name Functional Description 7 -4 TMA1-4 Transmit Multiframe Alignment Bits One to Four. These bits are (0) transmitted on the PCM 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero of every signalling multiframe. These bits are used by the far end to ...
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... See Loopbacks section. 0 PLBK Payload Loopback. If one, then all time slots received on RTIP/RRING (0) are connected to TTIP/TRING on the ST-BUS side of the MT9075B (this excludes time slot zero). If zero, then this feature is disabled. Table 18 - Coding and Loopback Control Word (Page 01H, Address 15H) Bit Name ...
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... MT9075B Bit Name Functional Description 7 --- Unused. 6 PRBSO PRBS Counter Interrupt. When (0) (PRBSO = 1), an interrupt is initiated on overflow of PRBS counter (page 04H, address 10H) from FFH to 0H. Interrupt vector = 00000010. 5 PRBSI PRBS Interrupt. When unmasked (PRBSI = 1), an interrupt is initiated ( single PRBS detection error. ...
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... FERI (0) 1 BPVO (0) 0 SLPI (0) Table 22 - Interrupt Mask Word Zero (Page 01H, Address 1BH) MT9075B Functional Description Synchronization Interrupt. When unmasked (SYNI = 0) an interrupt is initiated when a loss of basic frame synchronization condition exists. Interrupt vector = 10000000. Remote Alarm Indication Interrupt. When unmasked (RAII = 0) a received RAI will initiate an interrupt ...
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... MT9075B Bit Name Functional Description 7 EBI Receive E-bit Interrupt. When unmasked an interrupt is initiated (0) when a receive E-bit indicates a remote CRC-4 unmasked masked. Interrupt vector = 00100000. 6 CRCI CRC-4 Error unmasked an interrupt is initiated (0) when a local CRC-4 error occurs unmasked masked. Interrupt vector = 00100000. 5 CEFI Consecutively Interrupt ...
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... Table 25: Interrupt Mask Word Three Synchronization unmasked multiframe Multiframe = 1), an signalling signal is vector = MT9075B Functional Description One Second Status Interrupt. When unmasked (1SECI = 1), an interrupt is initiated when the 1SEC status bit (page 03H, address 12H, bit 7) changes from zero to one. Interrupt vector = 00001000. ...
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... MT9075B Address ( 10H (Table 28) Error and Debounce Selection Word 11H --- 12H --- 13H (Table 29) Access Control Word 14H --- 15H --- 16H --- 17H --- 18H (Table 30) Jitter Attenuator Control Word 19H (Table 31) Receive Equalization Control Word 1AH Reserved 1BH Reserved ...
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... PCM 30 data. A one, zero or one-to-zero transition has no function. Loss of Signal Error Insertion. If one, the MT9075B transmits an all zeros signal (no pulses) in every PCM 30 time slot. If zero, data is transmitted normally. Payload Error Insertion. A zero-to- one transition of this bit inserts a single error in the transmit payload ...
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... GCI/ST GCI or ST-BUS Frame Pulse. If one, the MT9075B will transmit or (0) receive a GCI frame pulse on pin F0b (pin 46 in PLCC MQFP). If zero, the MT9075B will transmit or receive an ST-BUS frame pulse on F0b. Table 29 - Access Control Word (Page 02H, Address 13H) 40 Preliminary Information ...
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... CPLD6 ( CPLD5- CPLD0 (000000) Table 35 - Custom Pulse Level 4 (Page 2, Address 1FH) MT9075B Functional Description Sign bit. Normalized to a positive going one, when CPLB6 is one then the CPLB0-CPLB5 coefficient corresponds to a positive level. When CPLB6 is zero the coefficient is taken to indicate a negative level. ...
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... MT9075B Master Status 1 (Page 03H) Address Register ( 10H (Table 37) Synchronization Status Word 11H (Table 38) Receive Frame Alignment Signal 12H (Table 39) Timer Status 13H (Table 40) Receive Non-frame Alignment Signal 14H (Table 41) Receive Multiframe Alignment Signal 15H (Table 42) ...
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... CRC-4 Table 38 - Receive Frame Alignment Signal (Page 03H, Address 11H) basic frame CRCIWK MT9075B Functional Description Receive International Use Zero. This is the bit which is received on the PCM 30 2048 kbit/sec. link in bit position one of the frame alignment signal used for the CRC-4 remainder or for international use ...
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... This bit shall be low when T2 becomes high. Refer to I.431 Section 5.9.2.2. Timer Two. This bit will be high when the MT9075B terminal frame persisting for 10 msec. This bit shall be low when operational frames are received. I.431 Section 5.9.2.2.3. ...
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... Table 42 - Most Significant Phase Status Word (Page 03H, Address 15H) MT9075B Functional Description network clock. If zero, pattern is not ...
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... MT9075B Bit Name Functional Description RxEBC7 -0 Receive Eighth Bit Count. The 8 least significant bit of a counter that indicates the number of one eighth bit times there are between the ST-BUS frame pulse and receive frame pulse (RxFP).The accuracy of the this measurement is approximately + 1/16 (one sixteenth bit ...
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... Signal 16 Bit Name operation ID7-0 detection is MT9075B Functional Description Remote Alarm Indication Status. If one, there is currently a remote alarm condition (i.e., received A bit is one). If zero, normal operation. Updated on a non-frame alignment frame basis. RAI and Continuous CRC Error Status. If one, there is currently an RAI and continuous CRC error condition ...
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... MT9075B Master Status 2 (Page 04H) Address ( 10H (Table 50) PRBS Error Counter 11H (Table 51) CRC Multiframe counter for PRBS 12H (Table 52) Interrupt Vector 13H (Table 53) E-bit Error Counter Ebt 14H (Table 54) E-bit Error Counter Ebt 15H (Table 55) ...
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... Name JFC7 JFC0 Counter for received CRC MT9075B Functional Description Jitter FIFO Counter. This bit counter that is incremented when - the FIFO read pointer comes within 4 words of an underflow or overflow condition. During this time the read clock will abruptly slow-down or speed-up to avoid an overflow or underflow condition ...
Page 50
... MT9075B Bit Name Functional Description 7 PRBSO PRBS Error Counter Overflow. This bit is set to one when the PRBS Error Counter (page 04H address 10H) cleared when this register is read. 6 FEBEO E Bit Counter Overflow. This bit is set to one when the E bit Counter (page 04H, address 13H & 14H) overflows ...
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... CC9- CC8 Bit Name CC7- CC0 MT9075B Functional Description BPV Counter. The most significant eight bits bit counter that is - incremented once for every bipolar violation error received. Functional Description BPV Counter. The least significant eight bits bit counter that is ...
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... MT9075B Per Channel Transmit Signalling (Page 05H) Table 62 describes Page 05H, addresses 11H to 1FH, which contains the Transmit Signalling Control Words for PCM 30 channels and 16 to 30. Control of these bits is through the processor or controller port when page 01H, address 1AH, bit 3, RPSIG = 1. ...
Page 53
... Receive Signalling Bits for Channel n + 15. These bits are received on the PCM 30 2048 kbit/sec. link in bit positions five to eight of time slot 16 in frame n (where 15), and are the signalling bits associated with channel n + 15. Unused - High impedance state. MT9075B 53 ...
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... MT9075B Per Time Slot Control Words (Pages 07H and 08H) The control functions described by Table 69 are repeated for each PCM-30 channel. Page 07H addresses 10H to 1FH correspond to time slots 0 to 15, while page 08H addresses 10H to 1FH correspond to time slots 16 to 31. ...
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... LSB Latched BPV Error Count (Table 79) 15H MSB Latched CRC Error Count (Table 80) 16H LSB Latched CRC Error Count (Table 81) 17H - 1FH - - - Table 74 - One Second Status (Page 09H) Register LEC9-LEC8 LEC7-LEC0 LEFAS7-LEFAS0 LBPV15-LBPV8 LBPV7-LBPV0 LCC9-LCC8 LCC7-LCC0 Unused. MT9075B Names 55 ...
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... MT9075B Bit Name Functional Description --- Unused LEC9 Latched E bit error counter (the most significant two bits). These - bits are sampled every second by LEC8 the internal one second timer. Table 75 - Latched E-bit Error Counter (Page 09H, Address 10H) Bit Name ...
Page 57
... Interrupt Status Ga, FA:Txunder, RxFf, RxOvfl Rx CRC MSB Crc15-Crc8 Rx CRC LSB Crc7-Crc0 --- Cnt7-Cnt0 --- HRST, RTloop, RSV, RSV, RSV, Ftst, RSV, Hloop Test Status RXclk, TXclk, Vcrc, Vaddr --- RFD2-0, TFD2-0 --- RFFS2-0, TFLS2-0 MT9075B Name EOPD, TEOP, EOPR, TxFl, EOPD, TEOP, EOPR, TxFl, 57 ...
Page 58
... MT9075B Bit Name Functional Description Adr16 A six bit mask used to interrogate the first byte of the received - address. Adr16 is the MSB. Adr11 (000000) 1 Adr10 This bit is used comparison, if control bit Seven, bit ( HDLC Control Register 2 (address 15H) is one. 0 A1en When this bit is high, this six (or ...
Page 59
... RQ9, RQ8 Byte Status bits from RX FIFO. Reset Table 88 - HDLC Status Register (Pages 0BH & 0CH, Address 14H) (Continued) MT9075B Functional Description When zero, the transmitter will idle state. When one interframe time fill state. These two states will only occur when the TX FIFO is empty ...
Page 60
... MT9075B Bit Name Functional Description 3, 2 Txstat2, Transmit Status. Txstat1 indicate the status of the TX FIFO as follows: Txsta Txsta FIFO full up to the selected status level or more. See Table 93. The number of bytes the TX FIFO has reached exceeded selected threshold level. See Table 94 ...
Page 61
... This register is updated at the end of each received packet and therefore should be read when end of packet is detected. Table 92 - Receive CRC MSB Register (Pages 0BH & 0CH, Address 18H) MT9075B byte RX FIFO bit first and 61 ...
Page 62
... MT9075B Bit Name Functional Description Crc7 - 0 The LSB byte of the CRC received from the transmitter. These bits are as the transmitter sent them; that is, most significant inverted. This register is updated at the end of each received packet and therefore should be read when end of packet is detected ...
Page 63
... Bit Name 7 --- RFD2 - 0 (000) the Address 3 --- TFD2 - 0 (000) Table 97 - HDLC Control Register 3 (Pages 0BH & 0CH, Address 1DH) MT9075B Functional Description Unused. These bits select the Rx FIFO full status level: RFD2 RFD1 RFD0 Full Status Level ...
Page 64
... MT9075B Bit Name Functional Description 7 --- Unused RFFS2 - 0 These bits select the RXFF (Rx FIFO Full) interrupt threshold level: (000) RFFS RFFS RFFS --- Unused TFLS2 - 0 These bits select the TXFL (Tx FIFO Low) interrupt threshold level: ...
Page 65
... Functional Description Bits Frames 1 to 15. This byte contains the bits received in bit a n MT9075B ...
Page 66
... MT9075B Page 0FH, addresses 10H to 1FH contain the 16 bytes of transmit message buffer zero Bit Name TxB0.n.7 - Transmit Bits This byte is transmit on a time slot when selected by the TXMSG bit of the appropriate per time slot control word and represents TxB0 ...
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... Sym Level 2 0 MT9075B Min Max Units -0 -55 125 ) unless otherwise stated. SS Units Test Conditions ˚ unless otherwise stated. SS Max Units Test Conditions 150 mA Outputs unloaded. ...
Page 68
... MT9075B AC Electrical Characteristics Characteristics 1 DS low 2 DS High 3 CS Setup 4 R/W Setup 5 Address Setup 6 CS Hold 7 R/W Hold 8 Address Hold 9 Data Delay Read 10 Data Hold Read 11 Data Active to High Z Delay 12 Data Setup Write 13 Data Hold Write * 14 Cycle Time † Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage ‡ ...
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... ADH t 80 DDR t 80 DAZ t 10 DSW t 10 DHW t 110 CYC t CYC t RDL t CSS t ADS t DDR VALID DATA t DSW VALID DATA MT9075B Units Test Conditions =50pF CSH CSH ADH t ADH ...
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... MT9075B AC Electrical Characteristics - Transmit Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Setup 3 Data Link Hold F0b TIME SLOT 0 Bits 4,3,2,1,0 TxDLCLK TxDL TxDLCLK TxDL Figure 13 - Transmit Data Link Functional Timing C4b TxDLCLK TxDL Figure 14 - Transmit Data Link Timing Diagram ...
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... Figure 15 - Receive Data Link Functional Timing E2o t RDC RxDLCLK t RDD RxDL Figure 16 - Receive Data Link Timing Diagram Sym Min Typ Max Units t 150 ns RDC RDD Example kb/s Example kb/s t RDC MT9075B Test Conditions 50pF 50pF TT TT ...
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... MT9075B AC Electrical Characteristics - Transmit 64 k Common Channel Timing Characteristic 1 Transmit Common Channel Setup 2 Transmit Common Channel Hold F0b STBUS Channel Times Internal Clock CSTi Figure 17 - Transmit 64k Common Channel Functional Timing C4b Internal Clock CSTi Figure 18 - Transmit 64k Common Channel Timing Diagram ...
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... Receive Common Channel Output Delay Rx64KCK CSTo Figure 19 - Receive 64k Common Channel Functional Timing Rx64KCK CSTo Figure 20 - Receive 64k Common Channel Timing Diagram Sym Min Typ Max t 60 RCD Receive Frame Boundary t RCD MT9075B Units Test Conditions ns 50pF TT ...
Page 74
... MT9075B AC Electrical Characteristics - ST-BUS / GCI Timing Characteristic 1 C4b Clock Width High or Low 2 C4b Clock Width High or Low 3 Frame Pulse Setup 4 Frame Pulse Hold 5 Frame Pulse Delay 6 Serial Input Setup 7 Serial Input Hold 8 Serial Output Delay ST-BUS Channel 31 Bit Cells Bit 0 F0b ...
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... Figure 23 - ST-BUS Timing Diagram (Output Clocks) ST-BUS Channel 31 Bit Cells Bit 0 F0b C4b Figure 24 - GCI Functional Timing Diagram Bit Cell Bit Cell t t 4WO FPD t t 4WO SIH t t SIS SOD Channel 0 Channel 0 Bit 7 Bit 6 MT9075B TT, CT Channel 0 Bit 5 75 ...
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... MT9075B ST-BUS Bit Bit Cell Stream F0b (Input) C4b (Input) All Input Streams All Output Streams Figure 25 - GCI Timing Diagram (Input Clocks) ST-BUS Bit Bit Cell Stream F0b (Output) t FPD C4b (Output) All Input Streams All Output Streams Figure 26 - GCI Timing Diagram (Output Clocks) ...
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... Figure 28 - Transmit Multiframe Functional Timing Sym Min Typ Max t 50 MOD Bit 4 Bit 0 Bit 7 Bit 6 Bit 4 Bit 0 Bit 7 Bit 6 MT9075B Units Test Conditions ns 50pF 256 C2 periods -100nsec Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 77 ...
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... MT9075B F0b t MOD C4b (1) RxMF t MS (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 29 - Multiframe Timing Diagram FRAME FRAME 15 0 TIME SLOT Most BIT Significant Bit (First) CHANNEL CHANNEL 0 31 Most Significant Bit (First MOD t MH 2.0 ms • ...