MT9075B Mitel Networks Corporation, MT9075B Datasheet - Page 40

• Manufacturer Part Number: MT9075B
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9075B
40
7-3
Bit
2
1
0
LOS/LOF
ADSEQ
GCI/ST
Name
(0)
(0)
(0)
--
Table 29 - Access Control Word
(Page 02H, Address 13H)
Unused.
Loss of Signal or Loss of Frame
Selection. If one, pin LOS (pin 61 in
PLCC, 57 in MQFP) will go high
when a loss of signal state exits
(criteria as per LLOS status bit on
page 03H address 18H). If low, pin
LOS will go high when either a loss
of signal (LLOST =1) or a loss of
basic frame alignment state exits
(bit SYNC on page 03H address
10H is zero).
Digital Milliwatt or Digital Test
Sequence. If one, the A-law digital
milliwatt analog test sequence will
be selected by the Per Time Slot
Control bits TTST and RTST (on
page 07H and 08H). If zero, the
PRBS 2
sequence will be selected by the
Per Time Slot Control bits TTST and
RTST. The PRBS generator is reset
whenever this bit is set to 1.
GCI or ST-BUS Frame Pulse. If
one, the MT9075B will transmit or
receive a GCI frame pulse on pin
F0b (pin 46 in PLCC, 34 in MQFP).
If zero, the MT9075B will transmit or
receive an ST-BUS frame pulse on
F0b.
Functional Description
15
-1 bit error rate test
4 - 2
Bit
7
6
5
1
0
Table 30 - Jitter Attenuator Control Word
JAT/JAR
Name
JFD2-
JFD0
JACL
JAS
JFC
(00)
(0)
(0)
(0)
(0)
---
(Page 02H, Address 18H)
Jitter Attenuator Select. If one,
the attenuator may be connected to
either the transmit or receive sides
of the PCM 30 interface depend on
bit 6 - JAT/JAR. If zero, the jitter
attenuator function is disabled.
Transmit
Attenuator.
attenuator will function on the
transmit data. If zero, the jitter
attenuator will function on the
receive data.
Jitter Attenuator FIFO Centre.
When this bit is toggled the read
pointer of the jitter attenuator shall
be centered. During centering the
jitter in the JA outputs is increased
by 0.0625 U.I
Jitter Attenuator FIFO Depth
Control Bits. These bits determine
the depth of the jitter attenuator
FIFO as shown below:
Jitter Attenuator Clear bit. If one,
the Jitter Attenuator, its FIFO and
status
registers will identify the FIFO as
being empty. However, the actual
bit values of the data in the JA
FIFO will not be reset.
Unused.
JFD2
0
0
0
0
1
1
1
1
Preliminary Information
Functional Description
are
JFD1
0
0
1
1
0
0
1
1
or
If
reset.
JFD0
Receive
one,
0
1
0
1
0
1
0
1
The
the
(words)
Depth
112
128
16
32
48
64
80
96
status
Jitter
jitter