MT90826 Mitel Networks Corporation, MT90826 Datasheet - Page 11

• Manufacturer Part Number: MT90826
• Description: Quad Digital Switch
• Manufacturer: Mitel Networks Corporation

Advanced Information
Memory Mapping
The address bus on the microprocessor interface
selects the internal registers and memories of the
MT90826. If the A13 address input is low, then the
registers are addressed by A12 to A0 according to
Table 3.
If the A13 is high, the remaining address input lines
are used to select location in the data or connection
memory depending upon MS bit in the control
register. For data memory reads, the serial inputs
are selected. For connection memory writes, the
serial outputs are selected. The destination stream
address bits and channel address bits are defined by
A12 to A8 and A7 to A0 respectively. See Table 4 for
the memory address mapping.
The control register controls all the major functions
of the device. It selects the internal memory
locations that specify the input and output channels
selected for switching and should be programmed
immediately after system power-up to establish the
desired switching configuration as explained in the
Frame Alignment Timing & Switching Configurations
sections.
The data in the control register consists of the block
programming bits (BPD0-2), the block programming
enable bit (BPE), the memory block programming bit
(MBP), the memory select bits (MS), the start frame
evaluation bit (SFE), the output stand by bit (OSB),
the wide frame pulse control bit (WFP) and the data
rate selection bits (DR0-2). See Table 5 for the
description of the control register bits.
Connection Memory Control
The connection memory controls the switching
configuration of the device. Locations in the
connection memory are associated with particular
STo output streams.
The TM0 and TM1 bits of each connection memory
location
throughput delay mode, the constant throughput
delay mode, the message mode or the bit error test
mode for all STo channels.
When the variable or constant throughput delay
mode is selected, (TM1=0/1, TM0=0), the contents of
the stream address bit (SAB) and the channel
address bit (CAB) of the connection memory defines
the source information (stream and channel) of the
timeslot that will be switched to the STo streams.
allows
the
selection
of
the
variable
When the message mode is selected, (TM1=0,
TM0=1) , only the lower half byte (8 least significant
bits) of the connection memory is transferred to the
associated STo output channel.
When the bit error test mode is selected, (TM1=1,
TM0=1), the pseudo random pattern will be output on
the associated STo output channel.
See Table 17 for the description of the connection
memory bits.
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to
indicate to the CPU that a data bus transfer is
complete. When the read or write cycle ends, this pin
changes to the high-impedance state.
Initialization of the MT90826
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90826
is in the normal functional mode. A 5K pull-down
resistor can be connected to the TRST pin so that
the device will not enter the JTAG test mode during
power up.
After power up, the contents of the connection
memory can be in any state. The ODE pin should be
held low after power up to keep all serial outputs in a
high impedance state until the microprocessor has
initialized the switching matrix. This procedure
prevents two serial outputs from driving the same
stream simultaneously.
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the switch. Users can also consider
using the memory block programming feature to
quickly initialize the OE, TM0 and TM1 bits in the
connection memory. When this process is complete,
the microprocessor controlling the matrices can
either bring the ODE pin high or enable the OSB bit
in control register to relinquish the high impedance
state control.
CMOS
MT90826
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