MT8880C Mitel Networks Corporation, MT8880C Datasheet - Page 4

• Manufacturer Part Number: MT8880C
• Description: Integrated DTMFTransceiver
• Manufacturer: Mitel Networks Corporation

MT8880C/MT8880C-1
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
(V
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives v
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
4-36
TSt
MT8880C/C-1
) of the steering logic to register the tone pair,
V
St/GT
Figure 5 - Basic Steering Circuit
DD
V
ESt
DD
GTP
t
t
GTA
GTP
R1
), v
= (R1C1) In (V
= (R1C1) In [V
c
reaches the threshold
Vc
c
C1
(see Figure 5) to
c
DD
DD
to V
/ (V
/ V
ISO
TSt
DD
DD
)
-V
TSt
. GT
2
-CMOS
)]
the
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
The value of t
Electrical Characteristics) and t
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
present (t
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
V
St/GT
ESt
V
St/GT
ESt
DD
DD
GTP
Figure 6 - Guard Time Adjustment
R1
R1
) and tone absent (t
DP
t
REC
is a device parameter (see AC
t
ID
R2
t
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA; (tGTP > tGTA)
=t
GTP
C1
R2
= t
t
C1
GTP
DA
DP
= (R
+t
= (R1C1) In [V
+t
t
t
GTA
GTA
GTA
P
GTP
C1) In [V
R
R
P
P
REC
= (R1C1) In (V
= (R p C1) In (V
= (R1R2) / (R1 + R2)
= (R1R2) / (R1 + R2)
GTA
is the minimum
DD
). This may be
DD
/ (V
/ (V
DD
DD
DD
DD
-V
/V
-V
/V
TSt
TSt
TSt
TSt
)]
)
)
)