ISL6219 Intersil Corporation, ISL6219 Datasheet - Page 12

• Manufacturer Part Number: ISL6219
• Description: Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
• Manufacturer: Intersil Corporation

designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications. See the application note
information on applications of this controller.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted on
either side; and the total board space available for power-
supply circuitry. Generally speaking, the most economical
solutions will be for each phase to handle between 15 and
20A. All-surface-mount designs will tend toward the lower
end of this current range and, if through-hole MOSFETs can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 30A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
1.5V
1.5V
FIGURE 10. DYNAMIC-VID WAVEFORMS FOR 500KHz
V
V
01110
REF
OUT
, 100mV/div
DS(ON)
, 100mV/div
ISL6219 BASED MULTI-PHASE BUCK
CONVERTER
). In Equation 7, I
00110
VID CHANGE OCCURS
ANYWHERE HERE
L,PP
12
5µs/div
is the peak-to-peak inductor
V
ID
, 5V/div
AN1018
M
is the maximum
for additional
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total power dissipated in each lower MOSFET is
approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependant
on switching frequency, the power calculation is somewhat
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET
does not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 9,
the required time for this commutation is t
associated power loss is P
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. In Equation 10, this transition occurs
over a time t
A third component involves the lower MOSFET’s reverse-
recovery charge, Q
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can recover all of Q
P
LOW 2 ,
P
LOW 1 ,
=
S
V
P
P
2
; and the length of dead times, t
D ON
UP 1 ,
, and the approximate the power loss is P
=
UP 2 ,
DS(ON)
(
IN
r
DS ON
) during switching. Since a substantially
≈
≈
)
rr
rr
(
f
V
S
V
; and the upper MOSFET r
. Since the inductor current has fully
IN
IN
losses, a large portion of the upper-


)
I
----- -



N



M
I
----- -
I
----- -



N
M
N
M
I
----- -
M
N
+
M
UP,1
+
, V
–



I
-------- -
PP
I
------------ -
2
2
I
------------ -
L PP
L PP
(
D(ON)
,
2
,
2
1 d
 t

.
–
d1
 t


 t








)
----
----
; the switching
2
+
2
+
1
2
L






I
------------------------------ -



L PP
and P
I
----- -
f
f
N
M
S
S
,
–
2
1
12
(
and the
rr
I
-------- -
1 d
PP
2
, it is conducted
D
d1
–
OUT



.
DS(ON)
t
and t
)
d2
/V
IN
d2
(EQ. 10)
(EQ. 7)
(EQ. 8)
(EQ. 9)
); and
, at
UP,2
.