ISL6219 Intersil Corporation, ISL6219 Datasheet - Page 9

• Manufacturer Part Number: ISL6219
• Description: Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
• Manufacturer: Intersil Corporation

have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, a proper
selection of the current sense resistors (R
introduces channel current unbalance into the system.
Increasing the value of R
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
OVERCURRENT PROTECTION
The average current, I
compared with a constant 75µA reference current. If the
average current at any time exceeds the reference current,
the comparator triggers the converter to shut down. All PWM
signals are placed in a high-impedance state which signals
the drivers to turn off both upper and lower MOSFETs. The
system remains in this state while the controller counts 2048
phase-clock cycles.
This is followed by a soft-start attempt (see Soft-Start). If the
soft-start attempt is successful, operation will continue as
normal. Should the soft-start attempt fail, the ISL6219
repeats the 2048-cycle wait period and follows with another
soft-start attempt. This hiccup mode of operation continues
indefinitely as shown in Figure 6 as long as the controller is
enabled or until the overcurrent condition resolves.
VOLTAGE REGULATION
The ISL6219 uses a digital to analog converter (DAC) to gen-
erate a reference voltage based on the logic signals at pins
VID4 to VID0. The DAC decodes the a 5-bit logic signal (VID)
into one of the discrete voltages shown in Table 1. Each VID
input offers a 20µA pull up to 2.5V for use with open-drain out-
puts. External pull-up resistors or active-high output stages
can augment the pull-up current sources, but a slight accu-
racy error can occur if they are pulled above 2.9V.
The integrating compensation network shown in Figure 7
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC).
V
FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT-
COMP
BALANCE ADJUSTMENT
+
I
ER
-
+
f(jω)
I
1
-
AVG
I
AVG
SAWTOOTH SIGNAL
ISEN
in Figure 5, is continually
÷
9
in the cooler channels and
N
+
-
ISEN
Σ
in Figure 4)
PWM1
I
I
3
2
FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE
R
FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE
VID4
0A
0V
FB
1
1
1
1
1
1
1
1
1
1
1
1
1
TABLE 1. VOLTAGE IDENTIFICATION CODES
V
V
EXTERNAL CIRCUIT
+
-
DROOP
OUT
R
C
VID3
REGULATION
1
1
1
1
1
1
1
1
0
0
0
0
0
C
C
COMP
VSEN
VID2
FB
1
1
1
1
0
0
0
0
1
1
1
1
0
5ms/DIV
ISL6219 INTERNAL CIRCUIT
OUTPUT CURRENT, 20A/DIV
VID1
I
AVG
1
1
0
0
1
1
0
0
1
1
0
0
1
OUTPUT VOLTAGE,
500mV/DIV
ERROR AMPLIFIER
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
-
REFERENCE
VOLTAGE(V
V
VDAC
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
COMP
Off
DAC
)