ISL6506B Intersil Corporation, ISL6506B Datasheet - Page 5

• Manufacturer Part Number: ISL6506B
• Description: Multiple Linear Power Controller
• Manufacturer: Intersil Corporation

Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time T0, 5V
(bias) is applied to the circuit. At time T1, the 5V
surpasses POR level. Time T2, one soft start interval after
T1, denotes the initiation of soft start. The 3.3V
brought up through the internal standby LDO through an
internal digital soft start function. Figure 4 shows the 5V
rail initiating a soft start at time T2 as well. The ISL6506A will
draw 7.5µA into the 5VDLSB for a duration of one soft start
period. This current will enhance the P-MOSFET (Q
to Typical Application Schematic) in a controlled manner. At
time T3, the 3.3V
is pulled down to ground. If the 5V
the level of the 5V
experience a sudden step as the P-MOSFET gate is fully
enhanced. The soft start profile of the 5VDUAL may be
altered by placing a capacitor between the gate and drain of
the P-MOSFET. Adding this capacitor will increase the gate
capacitance and slow down the start of the 5V
At time T4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp up. With the ISL6506/B
(Figure 3), the 5V
5V
The ISL6506A will already have the 5V
regulation (Figure 4). At time T5, the 12V
surpassed the 12V POR level. Time T6 is three soft start
cycles after the 12V POR level has been surpassed. At time
T6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q
ATX rails to the 3.3V
pin is forced to a high impedance state which will turn the
P-MOSFET (Q
the 3.3V
3.3V, 5V, 12V
5VDLSB
ATX
3V3DL
FIGURE 2. 5V
5VSB
5VDL
DLA
S3
S5
rail through the body diode of the N-MOSFET (Q
AUX
rail in sleep states in put in standby mode.
ISL6506A
2
) off. Finally, the internal LDO which regulates
DUAL
DUAL
DUAL
SB
DUAL
rail by time T3, then the rail will
AND 3.3V
is in regulation and the 5VDLSB pin
rail will begin to ramp up from the
and 5V
5
AUX
1
DUAL
DUAL
and Q
TIMING DIAGRAM;
DUAL
rails. The 5VDLSB
rail has not reached
ATX
3
) that connect the
ISL6506, ISL6506A, ISL6506B
rail in
rail has
DUAL
DUAL
SB
2
rail.
SB
rail is
, refer
DUAL
3
).
Sleep to Wake State Transitions
Figures 3 and 4, starting at time T4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506/B from the S4/S5 state to the S0
state. Figure 4 shows how the ISL6506/B will transition from
the S3 sleep state into S0 state. Figure 3 also shows how
the ISL6506A transitions from either S3 or S4/S5 in the S0
state. For all transitions, T4 depicts the system transition into
the S0 state. Here, the ATX supplies are enabled and begin
to ramp up. At time T5, the 12V
POR threshold for the ISL6506/B and ISL6506A. Three soft
start periods after time T5, at time T6, three events occur
0V
0V
FIGURE 4. SOFT START INTERVAL FOR ISL6506A IN S4/S5
FIGURE 3. ISL6506 and ISL6506B SOFT-START INTERVAL
T0
T0
(1V/DIV)
(1V/DIV)
5VSB
5VSB
T1
5VDLSB
T1
(5V/DIV)
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506/A/B
IN S4/S5 STATE AND S5 TO S0 TRANSITION
T2
T2
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VDUAL
(1V/DIV)
T3
T3
TIME
TIME
ATX
T4
T4
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T5
T5
rail has exceeded the
5VDUAL
(1V/DIV)
(10V/DIV)
(10V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
DLA
DLA
3.3VDUAL
(2V/DIV)
3.3VDUAL
(2V/DIV)
T6
T6