ISL6506B Intersil Corporation, ISL6506B Datasheet - Page 6

• Manufacturer Part Number: ISL6506B
• Description: Multiple Linear Power Controller
• Manufacturer: Intersil Corporation

simultaneously. The DLA pin is forced to a high impedance
state which allows the 12V rail to enhance the two N-
MOSFETs (Q
3.3V
high impedance state which will turn the P-MOSFET (Q
off. Finally, the internal LDO which regulates the 3.3V
rail in sleep states is put in standby mode.
Internal Linear Regulator Undervoltage Protection
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft start interval later, the 3.3V linear
regulator is retried with a soft start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
Internal Linear Regulator Over Current Protection
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced which causes
the output voltage of the linear regulator to be reduced.
When the output voltage is reduced to the undervoltage trip
point, the undervoltage protection is initiated and the output
will shutdown.
Layout Considerations
The typical application employing an ISL6506 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3V
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V
of current - for best results, ensure it is connected to its
respective source through an adequately sized trace and is
properly decoupled. The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
DUAL
and 5V
1
DUAL
and Q
DUAL
island or the I/O circuitry. Ensure the
3
) that connect the ATX rails to the
rails. The 5VDLSB pin is forced to a
6
SB
) carries a similar level
ISL6506, ISL6506A, ISL6506B
DUAL
2
)
electrolytics or tantalum capacitors) placement is not as
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
12VATX
+3.3VIN
Q2
FIGURE 5. PRINTED CIRCUIT BOARD ISLANDS
C
HF3V
KEY
3V3DUAL
C
5VSB
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
C
3V
VCC
3V3AUX
GND
ISL6506/A/B
5VSB
5VDLSB
EPAD
DLA
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C
5V
5VDUAL
CIN
C
Q4
Q3
HF5V
5VATX