ISL6524 Intersil Corporation, ISL6524 Datasheet - Page 11

• Manufacturer Part Number: ISL6524
• Description: VRM8.5 PWM and Triple Linear Power System Controller
• Manufacturer: Intersil Corporation

Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration for a
voltage-mode controller requiring external compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (V
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
The PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
+5V
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
OUT
V
+3.3V
OUT3
IN
+3.3V
V
OUT2
KEY
) is regulated to the Reference voltage level. The
IN
IN
C
C
L
SS24,13
OUT3
IN
C
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
C
IN
OUT2
OUT
ISLANDS
Q3
Q4
/V
E/A
+12V
. This function is dominated by a DC
DRIVE2
SS24
SS13
DRIVE3
VCC
C
VCC
ISL6524
PGND
11
GND
OCSET
DRIVE4
UGATE
PHASE
LGATE
IN
C
Q2
E/A
OCSET
at the PHASE node.
Q5
) is compared with
Q1
R
L
C
OCSET
CR1
OUT
C
OUT4
O
OUT1
and C
V
V
OUT4
OUT1
O
).
ISL6524
Gain, given by V
a double pole break frequency at F
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6524) and the impedance networks Z
Z
closed loop transfer function with high 0dB crossing frequency
(f
difference between the closed loop phase at f
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FB
0dB
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
LC
. The goal of the compensation network is to provide a
=
V
) and adequate phase margin. Phase margin is the
OSC
--------------------------------------- -
2
ST
ND
ST
ND
V
L
1
E/A
OSC
COMPENSATION DESIGN
O
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
IN
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
ISL6524
C
/V
O
COMP
OSC
PWM
Z
+
-
COMP
FB
-
+
C1
, and shaped by the output filter, with
REFERENCE
C2
DACOUT
+
-
R2
F
DRIVER
DRIVER
ESR
Z
IN
LC
=
FB
---------------------------------------- -
2
and a zero at F
Z
V
FB
IN
PHASE
ESR
(PARASITIC)
C3
1
0dB
Z
R1
L
IN
O
R3
and 180
C
ESR
O
C
V
O
OUT
ESR
LC
IN
V
o
)
OUT
and
.
.