ISL6564 Intersil Corporation, ISL6564 Datasheet - Page 17

• Manufacturer Part Number: ISL6564
• Description: Multiphase PWM Controller
• Manufacturer: Intersil Corporation

Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6564 checks the VID inputs at the three edges of
16MHz clock. If the VID code is found to have changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes sign, no change is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute step-up and step down VID
change at a speed of 12.5mV every 4µs until VID and DAC
are equal.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R
based voltage regulator. The selection of R
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C
duration for 1 bit VID change and the allowable delay time.
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
2.0V
WITH ISL6564CR
VCC
+
-
REF
0.5V
and C
E/A
GND
+
-
REF
FB
17
is required for an ISL6564
REF
DYNAMIC
VID D/A
is based on the time
ISL6564CR
REF
is based on
OFS
DAC
GND
VCC
OR
REF
R
R
REF
OFS
ISL6564
Assuming the microprocessor controls the VID change at 1
bit every T
R
Where, T
change cycle. If Typically R
allowable delay time for VR to respond to new VID code is 5
VID change cycles (totally 20µs), the value of C
be 22nF based on Equation 12.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, PGOOD asserts
logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6564 is
released from shutdown mode.
C
1. The bias voltage applied at VCC must reach the internal
REF
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
REF
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6564 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6564 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
CIRCUIT
and C
R
POR
FAULT LOGIC
SOFT START
REF
VID
VID
AND
ISL6564 INTERNAL CIRCUIT
REF
=
= 4µs, k is the number of the internal VID
SENSITIVE ENABLE (EN) FUNCTION
, the relationship between the time constant of
k T
network and T
VID
ENABLE
COMPARATOR
REF
+
-
1.23V
VID
is selected to be 1kΩ, the
is given by Equation 12.
VCC
EN
ENLL
EXTERNAL CIRCUIT
10.7kΩ
1.40kΩ
December 27, 2004
REF
+12V
should
(EQ. 12)
FN9156.2