GT28F160B3-B120 Intel Corporation, GT28F160B3-B120 Datasheet - Page 15

• Manufacturer Part Number: GT28F160B3-B120
• Description: SMART 3 ADVANCED BOOT BLOCK WORD-WIDE
• Manufacturer: Intel Corporation

3.1.1
The flash memory has three read modes available:
read array, read identifier, and read status. These
modes are accessible independent of the V
voltage. The appropriate read mode command must
be issued to the CUI to enter the corresponding
mode. Upon initial device power-up or after exit
from
automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output (DQ
drives the selected memory data onto the I/O bus.
For all read modes, WE# and RP# must be at V
Figure 15 illustrates a read cycle.
3.1.2
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.1.3
Deselecting the device by bringing CE# to a logic-
high level (V
which
consumption. In standby, outputs DQ
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device continues to consume active
power until the program or erase operation is
complete.
3.1.4
RP# at V
sometimes referred to as reset mode.
From read mode, RP# going low for time t
accomplishes the following:
1.
2.
PRELIMINARY
deselects the memory
places output drivers in a high-impedance
state
deep
substantially
IL
READ
OUTPUT DISABLE
STANDBY
DEEP POWER-DOWN / RESET
IH
initiates the deep power-down mode,
) places the device in standby mode,
power-down
reduces
0
–DQ
mode,
15
device
) control and it
IH
), the device
the
0
0
–DQ
–DQ
device
15
15
power
PLPH
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
are
are
IH
PP
.
After return from power-down, a time t
required until the initial memory access outputs are
valid. A delay (t
return from power-down before a write sequence
can be initiated. After this wake-up interval, normal
operation is restored. The CUI resets to read array
mode, and the status register is set to 80H (ready).
If RP# is taken low for time t
or erase operation, the operation will be aborted
and the memory contents at the aborted location
are no longer valid. After returning from an aborted
operation, time t
before a read or write operation is initiated
respectively.
3.1.5
A write is any command that alters the contents of
the memory array. There are two write commands:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to V
appropriate suspend command).
The Command User Interface does not occupy an
addressable memory location. Instead, commands
are
microprocessor write timings when WE# and CE#
are low, OE# = V
data (command) are presented. The command is
latched on the rising edge of the first WE# or CE#
pulse, whichever occurs first. Figure 16 illustrates a
write operation.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the
available commands. Appendix B provides detailed
information on moving between the different modes
of operation.
3.2
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. Three additional modes
written
Modes of Operation
WRITE
into
PHQV
PHWL
IH
, and the proper address and
the
or t
or t
PHWL
PHEL
CUI
PLPH
/t
) is required after
PHEL
IL
during a program
using
for t
must be met
PLRH
standard
PHQV
or an
15
is