IDT5T2010 Integrated Device Technology, IDT5T2010 Datasheet - Page 17

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IDT5T2010

Manufacturer Part Number
IDT5T2010
Description
2.5v Zero Delay Pll Clock Driver Teraclock
Manufacturer
Integrated Device Technology
Datasheet

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AC DIFFERENTIAL INPUT SPECIFICATIONS
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
LVEPECL
NOTES:
1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
3. Differential mode only. V
4. For single-ended operation, REF
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
Symbol
by V
The AC differential voltage must be achieved to guarantee switching to a new state.
V
V
V
V
V
V
t
DIF
DIF
W
IH
IL
IH
IL
DIF
has been met or exceeded.
Parameter
Reference/Feedback Input Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)
AC Differential Voltage
AC Input HIGH
AC Input LOW
AC Differential Voltage
AC Input HIGH
AC Input LOW
DIF
specifies the minimum input voltage (V
[1:0]
(4,6)
(4)
(4)
(4,5)
/V
REF
(3)
(3)
[1:0]
is tied to the DC voltage V
TR
- V
REF
CP
[1:0]
) required for switching where V
. Refer to each input interface's DC specification for the correct V
17
(1)
(2)
TR
(2)
is the "true" input level and V
Vx + 200
Min.
1275
400
400
INDUSTRIAL TEMPERATURE RANGE
1
1
Typ.
CP
is the "complement" input level.
REF
[1:0]
Vx - 200
Max
875
range.
Unit
mV
mV
mV
mV
mV
mV
ns

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