TDA7571 STMicroelectronics, TDA7571 Datasheet - Page 16

• Manufacturer Part Number: TDA7571
• Description: STPDACsw - Fully digital high efficiency power audio amplifier
• Manufacturer: STMicroelectronics

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Functions, pins and components description
4.6
4.7
16/21
Rs-P-L, Cs-P-L
Rs-N-R, Cs-N-R
Rs-P-R, Cs-P-R
Are in the direction to increase the dumping (point 1) and reduce the dv/dt (point 2).
The value of these components is also depending on the layout structure. With a reduction
of the parasitic inductance present in the P.C. board layout, in the region around the power
transistors, the value of these components can be reduced, giving advantage in terms of
THD, mainly at mid-high power levels, due to the reduction of the "dead zone".
The minimum suggested value of Rd-x-x is around 10 Ohm, while, is some cases, Rs-x-x
and Cs-x-x can be removed.
PLL
In case of the schematic shown in
at the Master Clock input frequency (MCLK).
The loop filter of this PLL is externally connected to the pin F (39). It consists in a lag-lead
filter (Cpll1, Rpll). The output resistance of the pin F is a 10K (typ) resistor.
The typical suggested values of Cpll1 and Rpll are the following:
Cpll1 = 10Kpf
Rpll = 1Kohm.
In some cases, in a system with few clock interactions and a good MCLK signal, a parallel
capacitor Cpll2 of 2.2nF-4.7nF can help to decrease the noise at the pin F.
With the PLL option, the A.C. output amplitude is not dependant by the resistor Rosc,
because the voltage across Rosc is defined by the PLL itself, Moreover, the output A.C.
voltage is independent also from the clock of the PCM signal (32kHz, 44.1kHz, 48kHz).
Vice versa, if the free running oscillation is selected, the output signal is dependant by the
Rosc value and from the input PCM frequency.
Dither
With the pins D1 (43) and D2 (44) 4 types of digital dithering is achievable:
Table 7.
Because of the recorded signals (music or speech) already contains some amount of noise,
the dithering is generally not needed.
For high quality signals, it is suggested do not use the cases 3 and 4, that can be useful only
in case of low resolution signals without noise added.
1
2
3
4
4 types of digital dithering
D1
0
0
1
1
Figure
3, the internal oscillator is locked by a PLL circuit
D2
0
1
0
1
Dithering
Mid-high
Mid-low
High
Low
TDA7571