UPD784035YGC NEC, UPD784035YGC Datasheet
UPD784035YGC
Related parts for UPD784035YGC
UPD784035YGC Summary of contents
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PD784035Y,784036Y,784037Y,784038Y 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD784038Y is based on the PD784038 with an I applications. One-time PROM and EPROM versions, such as the PD78P4038Y, that can operate in the same voltage range as mask ROM versions, and various development ...
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ORDERING INFORMATION Part Number PD784035YGC- -3B9 80-pin plastic QFP (14 PD784035YGC- -8BT 80-pin plastic QFP (14 Note PD784035YGK- -BE9 80-pin plastic TQFP (fine pitch) (12 PD784036YGC- -3B9 80-pin plastic QFP (14 PD784036YGC- -8BT 80-pin plastic QFP (14 Note PD784036YGK- -BE9 ...
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Series Product Development : Under mass production : Under development Standard models PD784026 A/D, 16-bit timer, enhanced power management ASSP models PD784908 TM On-chip IEBus controller PD78F4943 56-Kbyte flash memory for CD-ROM PD784915 Software servo control On-chip analog circuit ...
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FUNCTIONS Part Number PD784035Y Item Number of basic instructions 113 (mnemonics) General-purpose register 8 bits Minimum instruction execution 125 ns/250 ns/500 ns/1000 ns (@ 32-MHz operation) time Internal memory ROM 48 KBytes RAM 2048 Bytes Memory space 1 MByte with ...
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... MAJOR DIFFERENCES FROM PD784026 SUBSERIES AND PD78234 SUBSERIES ........ 8 3. PIN CONFIGURATION (TOP VIEW) ............................................................................................. 9 4. BLOCK DIAGRAM ......................................................................................................................... 11 5. PIN FUNCTION ............................................................................................................................... 12 5.1 Port Pins ................................................................................................................................................ 12 5.2 Non-Port Pins ....................................................................................................................................... 14 5.3 Types of Pin I/O Circuits and Connections for Unused Pins ........................................................ 16 6. CPU ARCHITECTURE ................................................................................................................... 19 6.1 Memory Space ...................................................................................................................................... 19 6.2 CPU Registers ...................................................................................................................................... 24 6.2.1 General-purpose registers ........................................................................................................ 24 6.2.2 Control registers ........................................................................................................................ 25 6.2.3 Special function registers (SFRs) ...
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LOCAL BUS INTERFACE ............................................................................................................. 52 9.1 Memory Expansion .............................................................................................................................. 52 9.2 Memory Space ...................................................................................................................................... 53 9.3 Programmable Wait ............................................................................................................................. 54 9.4 Pseudo Static RAM Refresh Function .............................................................................................. 54 9.5 Bus Hold Function ............................................................................................................................... 54 10. STANDBY FUNCTION ................................................................................................................... 55 ...
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DIFFERENCES AMONG MODELS IN PD784038Y SUBSERIES The only difference among the PD784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory capacity. The PD78P4038Y is provided with a 128-KB one-time PROM or EPROM instead of the mask ROM of ...
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MAJOR DIFFERENCES FROM PD784026 SUBSERIES AND PD78234 SUBSERIES Series Name PD784038Y Subseries Item PD784038 Subseries Number of basic instructions 113 (mnemonics) Minimum instruction execution time 125 ns (@ 32-MHz operation) Memory space (program/data) 1 MByte combined Timer/counter 16-bit timer/counter ...
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... P05 17 P06 18 P07 19 P67/REFRQ/HLDAK Notes 1. Under development 2. TEST pin should be connected to V PD784035Y, 784036Y, 784037Y, 784038Y -3B9, 784037YGC- -3B9, 784038YGC- -8BT, 784037YGC- -8BT, 784038YGC- 12 mm) Note 1 -BE9 , 784037YGK- -BE9, 784038YGK- directly. ...
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A8 to A19 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK, ASCK2 : Asynchronous Serial Clock ASTB : Address Strobe AV : Analog Power Supply DD AV ...
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BLOCK DIAGRAM PROGRAMMABLE NMI INTERRUPT INTP0 to INTP5 CONTROLLER INTP3 TIMER/COUNTER0 TO0 (16 BITS) TO1 TIMER/COUNTER1 INTP0 (16 BITS) INTP1 INTP2/CI TIMER/COUNTER2 TO2 (16 BITS) TO3 TIMER3 (16 BITS) P00 to P03 REAL-TIME OUTPUT PORT P04 to P07 PWM0 ...
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... Pins set in input mode can be connected to internal pull-up resistors by software. Port 4 (P4): • 8-bit I/O port • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. • Can drive LEDs. Port 5 (P5): • 8-bit I/O port • ...
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... AN10 to AN17 PD784035Y, 784036Y, 784037Y, 784038Y Function Port6 (P6): • 8-bit I/O port • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. Port 7 (P7): • 8-bit I/O port • Can be set in input or output mode bitwise. 13 ...
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... Capture trigger signal of CR02 Conversion start trigger input to A/D converter Time-division address/data bus (for external memory connection) Higher address bus (for external memory connection) Higher address when address is extended (for external memory connection) Read strobe to external memory Write strobe to external memory Wait insertion ...
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... The potential of the V pin must be equal to that of the V SS0 PD784035Y, 784036Y, 784037Y, 784038Y Function Chip reset Crystal connection for system clock oscillation (Clock can also be input to X1). Analog voltage input to A/D converter Analog voltage output from D/A converter Reference voltage to A/D converter Reference voltage to D/A converter ...
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... Types of Pin I/O Circuits and Connections for Unused Pins Table 5-1 shows types of pin I/O circuits and the connections for unused pins. For the input/output circuit of each type, refer to Figure 5-1. Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins Pin Name I/O Circuit Type P00 to P07 ...
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... Caution Connect an I/O pin whose input/output mode is unstable to V (especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software). Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K Series, these numbers of some models are not serial (because some circuits are not provided to some models) ...
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Figure 5-1. Types of Pin I/O Circuits Type 1-A V DD0 SS0 Type 2 IN Schmitt trigger input with hysteresis characteristics Type 4-B V DD0 data P output N disable V Push-pull output that can go ...
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CPU ARCHITECTURE 6.1 Memory Space A memory space of 1 MByte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed ...
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Figure 6-1. Memory Map of PD784035Y On execution of LOCATION 0 instruction Note 1 External memory (960 KBytes Special function registers (SFR) ...
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Figure 6-2. Memory Map of PD784036Y On execution of LOCATION 0 instruction Note 1 External memory (960 KBytes Special function registers (SFR) ...
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Figure 6-3. Memory Map of PD784037Y On execution of LOCATION 0 instruction Note 1 External memory (928 KBytes Internal ROM (32768 Bytes) ...
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Figure 6-4. Memory Map of PD784038Y On execution of LOCATION 0 instruction Note 1 External memory (896 KBytes Internal ROM (65536 Bytes) ...
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CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for ...
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Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-6. Program Counter (PC) Format 19 PC (2) Program status word (PSW) This register holds ...
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... SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. • After reset .......................... Indicates the status of the register when the RESET signal has been input. 26 PD784035Y, 784036Y, 784037Y, 784038Y This symbol is reserved for NEC’s assembler : Read-only : Write-only ...
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Table 6-1. Special Function Registers (SFRs) Note Address Special Function Register (SFR) Name 0FF00H Port 0 0FF01H Port 1 0FF02H Port 2 0FF03H Port 3 0FF04H Port 4 0FF05H Port 5 0FF06H Port 6 0FF07H Port 7 0FF0EH Port 0 ...
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Note 1 Address Special Function Register (SFR) Name 0FF36H Capture register (timer/counter 0) 0FF38H Capture register L (timer/counter 1) 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register H (timer/counter 2) 0FF41H Port 1 ...
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Note 1 Address Special Function Register (SFR) Name 0FF84H Clocked serial interface mode register 1 0FF85H Clocked serial interface mode register 2 0FF86H Serial shift register 0FF88H Asynchronous serial interface mode register 0FF89H Asynchronous serial interface mode register 2 ASIM2 ...
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Note Address Special Function Register (SFR) Name 0FFCCH Refresh mode register 0FFCDH Refresh area specification register 0FFCFH Oscillation stabilization time specification register 0FFD0H- External SFR area 0FFDFH 0FFE0H Interrupt control register (INTP0) 0FFE1H Interrupt control register (INTP1) 0FFE2H Interrupt control ...
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... PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting. PD784035Y, 784036Y, 784037Y, 784038Y Figure 7-1. Port Configuration P00 Port 0 P07 ...
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... Clock Generation Circuit An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generation Circuit ...
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Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation • EXTC bit of OSTS = 1 PD784038Y X1 X2 PD74HC04, etc. Caution When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to ...
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Real-Time Output Port The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt result, pulses without jitter can be output. The real-time ...
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Timer/Counter Three units of timers/counters and one unit of timer are provided. Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units of timers/counters. Table 7-2. Operations of Timers/Counters Name ...
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Figure 7-5. Block Diagram of Timers/Counters Timer/counter Prescaler XX Edge detection INTP3 Timer/counter 1 Prescaler Event input INTP0 Edge detection Timer/counter Prescaler XX INTP2/CI Edge detection INTP2 INTP1 Edge detection Timer ...
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PWM Output (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of 62.5 kHz ( MHz) are provided. Both these PWM output channels can select ...
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A/D Converter An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided. This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion result register (ADCR). Therefore, high-speed, ...
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D/A Converter Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and have a resolution of 8 bits. The conversion method is of R-2R resistor ladder type. By writing a value to ...
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Serial Interface Three independent serial interface channels are provided. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) • Clocked serial interface (CSI) 1 • 3-wire serial I/O (IOE) • 2-wire serial I/O (IOE • bus ...
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Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following ...
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... This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines. Generally, a handshake line is necessary to check the communication state. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode SI1, SI2 ...
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Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. Figure 7-12. Block Diagram of Clocked Serial Interface SI0 Selector SO0/SDA N-ch ...
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... Generally, a handshake line is necessary to check the communication status. (2) 2-wire serial I/O mode This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA). Generally, a handshake line is necessary to check the communication status (Inter IC) bus mode ...
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Edge Detection Function The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of ...
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INTERRUPT FUNCTION As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Entity of Servicing Vectored interrupt Software Context switching ...
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Type Default Priority Name Software – BRK instruction BRKCS instruction Operand error Non-maskable – NMI WDT Maskable 0 (highest) INTP0 1 INTP1 2 INTP2 3 INTP3 4 INTC00 5 INTC01 6 INTC10 7 INTC11 8 INTC20 9 INTC21 10 INTC30 ...
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Vectored Interrupt Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following ...
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Context Switching When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in ...
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Application Example of Macro Service (1) Transfer of serial interface TxD Each time macro service request (INTST) is generated, the next transfer data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS ...
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Real-time output port INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two stepping motors ...
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... RD WR REFRQ AD0-AD7 ASTB Latch A8-A15 9.1 Memory Expansion The memory capacity can be expanded in seven steps, from 256 Bytes to 1 MByte, by connecting an external program memory and data memory. 52 PD784035Y, 784036Y, 784037Y, 784038Y PROM Pseudo SRAM PD27C1001A Data bus Address bus Gate array I/O expansion Centronics I/F, etc ...
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Memory Space The 1-MByte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and pseudo static RAM refresh function ...
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... Programmable Wait The memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop. ...
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STANDBY FUNCTION This function is to reduce the power dissipation of the chip, and can be used in the following modes: • HALT mode: Stops supply of the operating clock to the CPU. This mode is used in combination ...
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... Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system can be reset and started from any address. Set the contents of each register by program as necessary. The RESET input circuit has a noise reduction circuit to prevent malfunctioning due to noise. This noise reduction circuit is a sampling circuit by analog delay ...
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INSTRUCTION SET (1) 8-bit instructions (The instructions in parentheses are combinations realized by describing MOV, XCH, ADD, ADDC SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ...
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AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction ...
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WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-Bit Addressing Second Operand #imm24 WHL First Operand WHL (MOVG) (MOVG) (ADDG) (ADDG) ...
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Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions Second Operand CY First Operand CY saddr.bit MOV1 sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit Note Either the second ...
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Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A Parameter Symbol Supply voltage Input voltage V I Output voltage V O Low-level output I Per pin OL current Total of all output pins High-level output ...
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OPERATING CONDITIONS • Operating ambient temperature (T • Rising time and falling time (tr, tf) (at pins which are not specified 200 s • Power supply voltage and clock cycle time Figure 13-1. Power Supply Voltage and ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended Circuit Ceramic resonator or crystal resonator V X1 SS1 C1 External clock X1 HCMOS inverter Caution When using the system clock oscillator, wiring the area enclosed with the broken line should be carried out as ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended Circuit Ceramic resonator or crystal resonator V X1 SS1 C1 External clock X1 HCMOS inverter Caution When using the system clock oscillator, wiring the area enclosed with the broken line should be carried out as ...
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DC CHARACTERISTICS (T = – Parameter Symbol Low-level input voltage V For pins other than those described in Notes 1, 2, IL1 3, 4, and 6 V For pins described in Notes ...
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DC CHARACTERISTICS (T = – Parameter Symbol Input leakage current For pins other than pin X1 when EXTC = 0 Output leakage current supply ...
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AC CHARACTERISTICS (T = – (1) Read/write operation (1/2) Parameter Symbol Address setup time +5.0 V 10% SAST DD ASTB high-level width +5.0 V 10% WSTH DD Address hold ...
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Read/write operation (2/2) Parameter Symbol Data setup time ( +5.0 V 10% SODW DD Data hold time +5.0 V 10% HWOD DD Note (from WR ) ASTB delay time t DWST ...
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External wait timing Parameter Symbol WAIT input time from +5.0 V 10% DAWT DD address WAIT input time from +5.0 V 10% DSTWT DD ASTB WAIT hold time from +5.0 ...
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SERIAL OPERATION (T = – (1) CSI Parameter Symbol Serial clock cycle time t Input CYSK0 (SCK0) Output Serial clock low-level t Input WSKL0 width (SCK0) Output Serial clock high-level t Input WSKH0 width (SCK0) ...
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IOE1, IOE2 Parameter Symbol Serial clock cycle time t Input CYSK1 (SCK1, SCK2) Output Serial clock low-level t Input WSKL1 width (SCK1, SCK2) Output Serial clock high-level t Input WSKH1 width (SCK1, SCK2) Output SI1, SI2 setup time t ...
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CLOCK OUTPUT OPERATION Parameter Symbol CLKOUT cycle time t CYCL CLKOUT low-level width +5.0 V 10% CLL DD CLKOUT high-level width +5.0 V 10% CLH DD CLKOUT rising time +5.0 V ...
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A/D CONVERTER CHARACTERISTICS ( Parameter Symbol Resolution Note Total error Note Linearity calibration Quantization error Conversion time CONV Sampling time SAMP ...
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D/A CONVERTER CHARACTERISTICS (T Parameter Symbol Resolution Total error Load conditions Load conditions Settling time Load conditions Output resistance R DACS0 ...
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DATA RETENTION CHARACTERISTICS (T Parameter Symbol Data retention voltage V STOP mode DDDR Data retention current I V DDDR DDDR V DDDR V rising time t DD RVD V falling time t DD FVD V hold time t DD HVD ...
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TIMING WAVEFORM (1) Read operation t WSTH ASTB t SAST A8 to A19 AD0 to AD7 t DSTR t DAR RD (2) Write operation t WSTH ASTB t SAST t HSTLA A8 to A19 AD0 to AD7 t DSTW t ...
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HOLD TIMING ADTB A19, AD0 to AD7, RD FHQC HLDRQ t DHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB t DSTWT A8 to A19 AD0 to AD7 t DAWT RD WAIT (2) Write ...
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REFRESH TIMING WAVEFORM (1) Random read/write cycle t RC ASTB (2) When refresh memory is accessed for read and write at the same time ASTB RD, WR REFRQ (3) Refresh after read ASTB RD REFRQ (4) ...
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SERIAL OPERATION (1) CSI t WSKL0 SCK t CYSK0 ( HIGH SCL SDA DAT (3) IOE1, IOE2 t WSKL1 SCK (4) UART, UART2 ASCK, ...
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CLOCK OUTPUT TIMING CLKOUT t CLR INTERRUPT INPUT TIMING NMI INTP0 CI, INTP1 to INTP3 INTP4, INTP5 RESET INPUT TIMING RESET PD784035Y, 784036Y, 784037Y, 784038Y t t CLH CLL t CLF t CYCL t t WNIH WNIL t t WIT0H ...
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EXTERNAL CLOCK TIMING DATA RETENTION CHARACTERISTICS STOP mode setting HVD FVD RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) 82 PD784035Y, 784036Y, 784037Y, 784038Y t t WXH WXL t XF ...
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PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark The shape and ...
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PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material of the ...
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PIN PLASTIC TQFP (FINE PITCH NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material of the ...
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... For details on the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended, please consult an NEC representative. Caution The soldering conditions for the PD784035YGK- fined because these products are currently under development. ...
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Table 15-1. Soldering Conditions for Surface Mount Type (2/2) (3) PD784037YGK- -BE9: 80-pin plastic TQFP (fine-pitch) (12 PD784038YGK- -BE9: 80-pin plastic TQFP (fine-pitch) (12 Soldering Method Infrared ray reflow Package peak temperature: 235 C, Reflow time: 30 seconds or less ...
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... C compiler package common to 78K/IV Series Note 1 CC78K4-L C compiler library source file common to 78K/IV Series PROM writing tool PG-1500 PROM program writer PA-78P4026GC Programmer adapter connected to PG-1500 PA-78P4038GK PA-78P4026KK Note 2 PG-1500 controller PG-1500 control program Debugging tool IE-784000-R In-circuit emulator common to 78K/IV Series ...
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... HP9000 series 700 (HP-UX) base • SPARCstation (SunOS) base • Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038. 2. The TGK-080SDW is a product of TOKYO ELETECH CORPORATION (Tokyo, 03-5295-1661). Consult an NEC sales representative about purchasing. PD784035Y, 784036Y, 784037Y, 784038Y TM ) base TM TM ...
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APPENDIX B RELATED DOCUMENTS Documents related to device Document Name PD784031Y Data Sheet PD784035Y, 784036Y, 784037Y, 784038Y Data Sheet PD78P4038Y Data Sheet PD784038, 784038Y Subseries User’s Manual - Hardware PD784038Y Subseries Special Function Register Table 78K/IV Series User’s Manual - ...
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... Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Guide to Microcontroller-Related Products by Third Parties Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...