UPD784035YGC NEC, UPD784035YGC Datasheet - Page 47

• Manufacturer Part Number: UPD784035YGC
• Description: 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
• Manufacturer: NEC

Software
Non-maskable
Maskable
Remark ASI: asynchronous serial interface
Type
CSI: clocked serial interface
0 (highest)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 (lowest)
Default
Priority
–
–
BRK instruction
BRKCS instruction
Operand error
NMI
WDT
INTP0
INTP1
INTP2
INTP3
INTC00
INTC01
INTC10
INTC11
INTC20
INTC21
INTC30
INTP4
INTP5
INTAD
INTSER
INTSR
INTCSI1
INTST
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
INTSPC
Name
Table 8-2. Interrupt Sources
PD784035Y, 784036Y, 784037Y, 784038Y
Instruction execution
If result of exclusive OR between byte of
operand and byte is not FFH when “MOV
STBC, #byte”, “MOV WDM, #byte”, or
“LOCATION” instruction is executed
Detection of pin input edge
Overflow of watchdog timer
Detection of pin input edge
(TM1/TM1W capture trigger, TM1/TM1W
event counter input)
Detection of pin input edge
(TM2/TM2W capture trigger, TM2/TM2W
event counter input)
Detection of pin input edge
(TM2/TM2W capture trigger , TM2/TM2W
event counter input)
Detection of pin input edge
(TM0 capture trigger, TM0 event counter input)
Generation of TM0-CR00 match signal
Generation of TM0-CR01 match signal
Generation of TM1-CR10 match signal
(in 8-bit operation mode)
Generation of TM1W-CR10W match signal
(in 16-bit operation mode)
Generation of TM1-CR11 match signal
(in 8-bit operation mode)
Generation of TM1W-CR11W match signal
(in 16-bit operation mode)
Generation of TM2-CR20 match signal
(in 8-bit operation mode)
Generation of TM2W-CR20W match signal
(in 16-bit operation mode)
Generation of TM2-CR21 match signal
(in 8-bit operation mode)
Generation of TM2W-CR21W match signal
(in 16-bit operation mode)
Generation of TM3-CR30 match signal
(in 8-bit operation mode)
Generation of TM3W-CR30W match signal
(in 16-bit operation mode)
Detection of pin input edge
Detection of pin input edge
End of A/D conversion (transfer of ADCR)
Occurrence of ASI0 reception error
End of ASI0 reception or CSI1 transfer
End of ASI0 transfer
End of CSI1 transfer
Occurrence of ASI2 reception error
End of ASI2 reception or CSI2 transfer
End of ASI2 transfer
I
2
C bus stop condition interrupt
Source
Trigger
External
External
External
External
Internal/
Internal
Internal
Internal
–
Macro service
–
–
–
–
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