AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet
AN2505
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AN2505 Summary of contents
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... Broadcast Host DMA Write Throughput ..............10 5 Actual Throughput Versus Frequency ..................11 5.1 Single Read Versus Local Bus Frequency ............11 5.2 Single Write Versus Local Bus Frequency ...........12 5.3 Host DMA Read Versus Local Bus Frequency ....12 5.4 Host DMA Write Versus Local Bus Frequency ...13 6 Summary ...............................................................14 7 References .............................................................15 AN2505 ...
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Asynchronous DSI Connections and Timings The DSI operates in either asynchronous or synchronous mode. In asynchronous mode, the DSI functions in an SRAM-like mode that does not require the host to supply a clock to the slave MSC8102. In synchronous ...
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MSC8102 DSI Timings The DSI timings are different, depending on whether the host processor reads from the DSI, writes to the DSI, or broadcasts data to multiple DSIs on multiple DSPs. The DSI communicates via a dual-strobe or a ...
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Asynchronous DSI Connections and Timings 2.2.2 DSI Write Timings Figure 3 shows the timings for an asynchronous DSI write transaction as indicated in the MSC8102 Technical Data sheet. When the memory controller on the host processor is programmed, the MSC8102 ...
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HCS HA[11–29] HCID[0–4] HDST HRW HRDS HWBSn HD[0–63] Figure 4. DSI Asynchronous Broadcast Write Timings 2.2.4 DSI Timing Values The timing values associated with the preceding diagrams are listed in Table 1. These values are directly from the MSC8102 Technical ...
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Theoretical Throughput Table 1. DSI Asynchronous Mode Timing (Continued) No. Characteristics 111 Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD HTA at end of access released at logic 1 • DCR[HTADT • DCR[HTADT] = ...
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The DSI asynchronous read transaction, which is programmed into the MSC8101 UPM memory controller as a single read, requires 5 cycles with a system bus clock of 66 MHz. The throughput is calculated by adding the cycles of the UPM ...
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Actual Throughput • Throughput measurements for host DMA accesses are taken over an average of four transactions. • Throughput measurements for single reads and writes are taken over an average of four transactions. 4.2 Single Read Throughput The maximum DSI ...
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System Bus Clock Address HCS/CS4 HWBS0/PWE0 HTA/UPMWAIT 4.4 Broadcast Single Write Throughput The maximum DSI single broadcast write performance is based on consecutive writes to MSC8102 M2 memory. Figure 7 shows one broadcast write transaction obtained from the logic analyzer. ...
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Actual Throughput System Bus Clock Address HCS/CS4 HRW/POE HTA/UPMWAIT 4.6 Host DMA Write Throughput The maximum DSI host DMA write performance is calculated from the timing results shown in Figure 9. The figure shows the host clock, address lines, chip ...
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System Bus Clock Address HBCS/CS3 HWBS0/PWE0 Figure 10. Asynchronous Broadcast Host DMA Write 5 Actual Throughput Versus Frequency The observed maximum throughput for the asynchronous DSI reads and writes on the MSC8102ADS are given in Section 4. These numbers are ...
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Actual Throughput Versus Frequency 5.2 Single Write Versus Local Bus Frequency Figure 12 illustrates the DSI throughput for a single write transaction versus the local bus frequency of the MSC8102. The DSI operates on the basis of the local bus ...
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Figure 13. DSI Host DMA Read Throughput Versus MSC8102 Local Bus Frequency 5.4 Host DMA Write Versus Local Bus Frequency Figure 14 illustrates the DSI throughput for a host DMA ...
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Summary Figure 14. DSI Host DMA Write Throughput Versus MSC8102 Local Bus Frequency 6 Summary The throughput for the MSC8102 DSI asynchronous 64-bit mode is obtained by examining the signals ...
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References The following Freescale documents are available at the web site listed on the back cover of this document. • MSC8102 Reference Manual • MSC8102 Technical Data sheet • MSC8101 Reference Manual • MSC8101 Technical Data sheet • MSC8102 ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com AN2505 Rev. 1 10/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...